中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

33 records (took 0.017 seconds)

    Dual heat spreader panel assembly method for bumpless die-attach packages, packages containing same, and systems containing same
    1.
    发明授权
    Dual heat spreader panel assembly method for bumpless die-attach packages, packages containing same, and systems containing same 有权
    双散热器面板组装方法，用于无冲击的芯片附接封装，包含它的封装以及含有它的系统

    公开(公告)号：US07723164B2

    公开(公告)日：2010-05-25

    申请号：US11469581

    申请日：2006-09-01

    Applicant: Daoqiang Lu ,  Jiangqi He ,  Xiang Yin Zeng ,  Jiamiao Tang

    Inventor： Daoqiang Lu ,  Jiangqi He ,  Xiang Yin Zeng ,  Jiamiao Tang

    IPC: H01L21/00

    CPC classification number: H01L21/4882 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24227 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/97 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2224/83

    Abstract: A process includes mating a first heat spreader and a second heat spreader, such that the first heat spreader at a mating surface and second heat spreader at a mating surface become parallel and adjacent. The process includes placing a first die in a first die recess of the first heat spreader, and placing a second die in a second die recess in the second heat spreader. The process includes reflowing thermal interface material between each die and respective heat spreader. Thereafter, the process includes separating the first heat spreader and the second heat spreader. A package is achieved by the process, with reduced thicknesses. The package can be disposed onto a mounting substrate. The package can be assembled into a computing system.

    Abstract translation: 一种方法包括：配合第一散热器和第二散热器，使得匹配表面处的第一散热器和配合表面处的第二散热器变得平行和相邻。 该方法包括将第一模具放置在第一散热器的第一模具凹部中，以及将第二模具放置在第二散热器中的第二模具凹部中。 该方法包括在每个模具和相应的散热器之间回流热界面材料。 此后，该方法包括分离第一散热器和第二散热器。 通过该方法实现了包装，减小了厚度。 该封装可以设置在安装基板上。 该包装可以组装成一个计算系统。

    Reducing parasitic mutual capacitances
    3.
    发明授权
    Reducing parasitic mutual capacitances 有权
    减少寄生互电容

    公开(公告)号：US07535080B2

    公开(公告)日：2009-05-19

    申请号：US11174246

    申请日：2005-06-30

    Applicant: Xiang Yin Zeng ,  Jiangqi He ,  BaoShu Xu

    Inventor： Xiang Yin Zeng ,  Jiangqi He ,  BaoShu Xu

    IPC: H01L29/93

    CPC classification number: H01G4/33 ,  H01G4/236 ,  H01G4/38 ,  H01L23/66 ,  H01L2223/6677 ,  H01L2224/16 ,  H01L2924/01019 ,  H01L2924/09701 ,  H01L2924/3025 ,  H05K1/162

    Abstract: A method to reduce parasitic mutual capacitances in embedded passives. A first capacitor is formed by first and second electrodes embedding a dielectric layer. A second capacitor is formed by third and fourth electrodes embedding the dielectric layer. The third and first electrodes are etched from a first metal layer. The fourth and second electrodes are etched from a second metal layer. The first and the fourth electrodes are connected by a connection through the dielectric layer to shield a mutual capacitance between the first and second capacitors.

    Abstract translation: 一种降低嵌入式无源器件中寄生互电容的方法。 第一电容器由嵌入电介质层的第一和第二电极形成。 第二电容器由嵌入电介质层的第三电极和第四电极形成。 从第一金属层蚀刻第三和第一电极。 从第二金属层蚀刻第四和第二电极。 第一和第四电极通过介电层的连接来连接，以屏蔽第一和第二电容器之间的互电容。

    Package level integration of antenna and RF front-end module
    4.
    发明授权
    Package level integration of antenna and RF front-end module 有权
    天线和RF前端模块的封装级集成

    公开(公告)号：US07477197B2

    公开(公告)日：2009-01-13

    申请号：US11618046

    申请日：2006-12-29

    Applicant: Xiang Yin Zeng ,  Jiangqi He ,  Guizhen Zheng

    Inventor： Xiang Yin Zeng ,  Jiangqi He ,  Guizhen Zheng

    IPC: H01Q1/38

    CPC classification number: H01Q1/2283 ,  H01L2223/6677 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/15321 ,  H01L2924/16152 ,  H01L2924/19105 ,  H01L2924/3025 ,  H05K1/0218 ,  H05K1/0298 ,  H05K1/141 ,  H05K1/16 ,  H05K3/3436 ,  H05K2201/0723 ,  H05K2201/10477 ,  H01L2924/00014

    Abstract: Electronic devices and methods for their formation are described. One device relates to an electronic assembly including a substrate having a first surface and a second surface opposite the first surface. The electronic assembly also includes at least one RF front-end module coupled to the first surface of the substrate, and a ground plane layer positioned on the second surface of the substrate. The electronic assembly also includes an insulating layer on the ground plane layer, with the ground plane layer positioned between the second surface and the insulating layer. In addition, the electronic assembly also includes an antenna layer on the insulating layer, with the insulating layer positioned between the antenna layer and the ground plane layer.

    Abstract translation: 描述了用于其形成的电子装置和方法。 一种装置涉及一种电子组件，其包括具有第一表面和与第一表面相对的第二表面的基底。 电子组件还包括耦合到衬底的第一表面的至少一个RF前端模块和位于衬底的第二表面上的接地平面层。 电子组件还包括在接地平面层上的绝缘层，其中接地平面层位于第二表面和绝缘层之间。 此外，电子组件还包括在绝缘层上的天线层，绝缘层位于天线层和接地平面层之间。

    IC package with signal land pads
    8.
    发明授权
    IC package with signal land pads 有权
    IC封装带信号焊盘

    公开(公告)号：US07227247B2

    公开(公告)日：2007-06-05

    申请号：US11060104

    申请日：2005-02-16

    Applicant: Xiang Yin Zeng ,  Jiangqi He ,  BaoShu Xu

    Inventor： Xiang Yin Zeng ,  Jiangqi He ,  BaoShu Xu

    IPC: H01L23/02

    CPC classification number: H01L23/49822 ,  H01L23/50 ,  H01L23/66 ,  H01L2223/6616 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/15173 ,  H01L2924/15174 ,  H01L2924/15313

    Abstract: In one embodiment, an integrated circuit package comprises a substrate including a first surface having a plurality of signal land pads and a second surface having a plurality of signal die pads; a plurality of signal connectors arranged to electrically couple the plurality of the signal land pads to the plurality of the signal die pads; and a ground plane, disposed in an adjacent, spaced-apart relationship to the plurality of signal land pads. The ground plane includes a plurality of holes with at least one of the holes having at least one of the signal connectors extending therethrough and being dimensioned and configured approximately to be as large or larger than at least one of the signal land pads disposed adjacent to the at least one hole.

    Abstract translation: 在一个实施例中，集成电路封装包括：衬底，其包括具有多个信号焊盘的第一表面和具有多个信号管芯焊盘的第二表面; 多个信号连接器，其布置成将多个信号焊盘区电耦合到多个信号管芯焊盘; 以及接地平面，与多个信号焊盘相邻设置成间隔开的关系。 接地平面包括多个孔，其中至少一个孔具有延伸穿过其中的信号连接器中的至少一个，其尺寸和构造近似大于或大于与邻近 至少有一个洞。

    Packaged spiral inductor structures, processes of making same, and systems containing same
    9.
    发明授权
    Packaged spiral inductor structures, processes of making same, and systems containing same 有权
    封装的螺旋电感器结构，制造方法以及含有它们的系统

    公开(公告)号：US07852189B2

    公开(公告)日：2010-12-14

    申请号：US11323339

    申请日：2005-12-30

    Applicant: Jiangqi He ,  Robert L. Sankman ,  BaoShu Xu ,  Xiang Yin Zeng

    Inventor： Jiangqi He ,  Robert L. Sankman ,  BaoShu Xu ,  Xiang Yin Zeng

    IPC: H01F27/28

    CPC classification number: H01F17/0006 ,  H01F27/323 ,  H01F41/041 ,  H01F2017/0046 ,  H01L23/5227 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A spiral inductor is disposed above a substrate that includes two different materials. A dielectric film is the first material that provides structural integrity for the substrate. A second dielectric is the second material that provides a low dielectric-constant (low-K) material closest to the spiral inductor coil. A process of forming the spiral inductor includes patterning the substrate to allow a recess as a receptacle for the second dielectric, followed by forming the spiral inductor mostly above the second dielectric.

    Abstract translation: 螺旋电感器设置在包括两种不同材料的衬底之上。 电介质膜是为衬底提供结构完整性的第一种材料。 第二介质是提供最接近螺旋电感线圈的低介电常数（低K）材料的第二材料。 形成螺旋电感器的过程包括图案化衬底以允许凹槽作为用于第二电介质的插座，随后形成主要位于第二电介质上方的螺旋电感器。

Patent Agency Ranking