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    Package board, semiconductor package, and fabricating method thereof
    3.
    发明申请
    Package board, semiconductor package, and fabricating method thereof 有权
    封装板，半导体封装及其制造方法

    公开(公告)号：US20070080469A1

    公开(公告)日：2007-04-12

    申请号：US11528324

    申请日：2006-09-28

    Applicant: Seung-Gu Kim ,  Je-Gwang Yoo ,  Yong-Bin Lee ,  Yoo-Keum Wee ,  Seok-Hwan Huh ,  Chang-Sup Ryu

    Inventor： Seung-Gu Kim ,  Je-Gwang Yoo ,  Yong-Bin Lee ,  Yoo-Keum Wee ,  Seok-Hwan Huh ,  Chang-Sup Ryu

    IPC: H01L23/48

    CPC classification number: H01L21/563 ,  H01L2224/73203 ,  H01L2924/0102 ,  H01L2924/01078

    Abstract: With a semiconductor package according to an aspect of the present invention comprising a board having circuit lines, solder resist formed on a surface of the board, and a chip mounted on the board and having at least one bump attached to at least a portion of the circuit lines, where the solder resist comprises a perimeter groove, which exposes at least a portion of the circuit lines, and an extension groove, which is connected to the perimeter groove, and where encapsulant is filled in the perimeter groove and the extension groove, the filling characteristics of the encapsulant is improved for greater reliability in the electrical connections between the chip and the board.

    Abstract translation: 根据本发明的一个方面的半导体封装，其包括具有电路线的板，形成在所述板的表面上的阻焊剂和安装在所述板上的芯片，并且具有附着到所述板的至少一部分上的至少一个凸块 电路线，其中阻焊剂包括暴露至少一部分电路线的周边凹槽和连接到周边凹槽的延伸凹槽，并且其中密封剂填充在周边凹槽和延伸凹槽中， 提高了密封剂的填充特性，以便在芯片和电路板之间的电连接中获得更高的可靠性。

    Package board, semiconductor package, and fabricating method thereof
    4.
    发明授权
    Package board, semiconductor package, and fabricating method thereof 有权
    封装板，半导体封装及其制造方法

    公开(公告)号：US07592708B2

    公开(公告)日：2009-09-22

    申请号：US11528324

    申请日：2006-09-28

    Applicant: Seung-Gu Kim ,  Je-Gwang Yoo ,  Yong-Bin Lee ,  Yoo-Keum Wee ,  Seok-Hwan Huh ,  Chang-Sup Ryu

    Inventor： Seung-Gu Kim ,  Je-Gwang Yoo ,  Yong-Bin Lee ,  Yoo-Keum Wee ,  Seok-Hwan Huh ,  Chang-Sup Ryu

    IPC: H01L21/31 ,  H01L21/469

    CPC classification number: H01L21/563 ,  H01L2224/73203 ,  H01L2924/0102 ,  H01L2924/01078

    Abstract: With a semiconductor package according to an aspect of the present invention comprising a board having circuit lines, solder resist formed on a surface of the board, and a chip mounted on the board and having at least one bump attached to at least a portion of the circuit lines, where the solder resist comprises a perimeter groove, which exposes at least a portion of the circuit lines, and an extension groove, which is connected to the perimeter groove, and where encapsulant is filled in the perimeter groove and the extension groove, the filling characteristics of the encapsulant is improved for greater reliability in the electrical connections between the chip and the board.

    Abstract translation: 根据本发明的一个方面的半导体封装，其包括具有电路线的板，形成在所述板的表面上的阻焊剂和安装在所述板上的芯片，并且具有附着到所述板的至少一部分上的至少一个凸块 电路线，其中阻焊剂包括暴露至少一部分电路线的周边凹槽和连接到周边凹槽的延伸凹槽，并且其中密封剂填充在周边凹槽和延伸凹槽中， 提高了密封剂的填充特性，以便在芯片和电路板之间的电连接中获得更高的可靠性。

    Printed circuit board
    5.
    发明申请
    Printed circuit board 审中-公开
    印刷电路板

    公开(公告)号：US20090097220A1

    公开(公告)日：2009-04-16

    申请号：US12010749

    申请日：2008-01-29

    Applicant: Young-Mi Lee ,  Suk-Chang Hong ,  Yong-Bin Lee ,  Chin-Kwan Kim

    Inventor： Young-Mi Lee ,  Suk-Chang Hong ,  Yong-Bin Lee ,  Chin-Kwan Kim

    IPC: H05K1/02

    CPC classification number: H05K3/3452 ,  H01L23/49816 ,  H01L23/49838 ,  H01L2224/05552 ,  H01L2224/05567 ,  H05K2201/0989 ,  H05K2201/09909 ,  H05K2201/10734 ,  H05K2203/041 ,  H01L2924/00012

    Abstract: A printed circuit board is disclosed. The printed circuit board, which has at least one pad on which a solder ball is to be placed, includes a solder resist that covers a surface of the printed circuit board, an opening part that exposes the pad and supports the solder ball, and an extended portion formed in a perimeter of the opening part that allows an underfill to flow in between the printed circuit board and the solder ball. With this printed circuit board, the underfill can be filled in more readily between the printed circuit board and the solder balls, when mounting a component on the printed circuit board.

    Abstract translation: 公开了印刷电路板。 具有至少一个其上要放置焊球的焊盘的印刷电路板包括覆盖印刷电路板的表面的阻焊剂，露出焊盘并支撑焊球的开口部分，以及 延伸部分形成在开口部分的周边，允许底部填充物在印刷电路板和焊球之间流动。 使用该印刷电路板，当将部件安装在印刷电路板上时，底部填充物可以更容易地填充在印刷电路板和焊球之间。

    Manufacturing method package substrate
    6.
    发明申请
    Manufacturing method package substrate 审中-公开
    制造方法封装衬底

    公开(公告)号：US20070298546A1

    公开(公告)日：2007-12-27

    申请号：US11785093

    申请日：2007-04-13

    Applicant: Jong-Jin Lee ,  Sun-Moon Kim ,  Mi-Seon Shin ,  Yong-Bin Lee

    Inventor： Jong-Jin Lee ,  Sun-Moon Kim ,  Mi-Seon Shin ,  Yong-Bin Lee

    IPC: H01L21/00 ,  H01L21/44

    CPC classification number: H01L23/49816 ,  H01L21/4853 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/49838 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H05K3/243 ,  H05K3/28 ,  H05K3/3473 ,  H05K3/42 ,  H05K2203/043 ,  H05K2203/054 ,  H05K2203/1581 ,  H01L2224/05599

    Abstract: A manufacturing method of a package substrate is disclosed. The method for manufacturing a package substrate is by forming a bump on a bump pad in a core board, where a first circuit pattern including the bump pad is formed on one surface, a second circuit pattern electrically connected with the first circuit pattern is formed on the other surface, and a dielectric layer is selectively coated on the one surface such that the bump pad is exposed. The method includes layering a conductive layer on the other surface of the core board, coating a plating resist on the conductive layer, forming the bump by supplying electricity to the conductive layer to electroplate the bump pad, and removing the plating resist and the conductive layer. This makes it possible to omit the coining process and increase the density of the circuit by forming a fine bump by an electro tin plating method with small plating thickness deviation without designing additional plating bus lines, and improves the electrical performance without remaining plating bus lines.

    Abstract translation: 公开了封装基板的制造方法。 制造封装衬底的方法是通过在芯板上的凸块焊盘上形成凸块，其中在一个表面上形成包括凸点焊盘的第一电路图案，与第一电路图形电连接的第二电路图案形成在 另一表面和电介质层被选择性地涂覆在一个表面上，使得凸块焊盘露出。 该方法包括在芯板的另一个表面上层叠导电层，在导电层上涂覆电镀抗蚀剂，通过向导电层供电以形成凸块以电镀凸块焊盘，以及去除电镀抗蚀剂和导电层 。 这样可以省略压印过程，并且通过在不设计附加的电镀母线的情况下通过电镀镀层方法形成微小的凸起来提高电路的密度，并且不需要剩余的电镀母线即可提高电气性能。

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