公开(公告)号：US20190129718A1

公开(公告)日：2019-05-02

申请号：US15799560

申请日：2017-10-31

Applicant: Advanced Micro Devices, Inc.

Inventor： Jiasheng Chen ,  Bin He ,  Yunxiao Zou ,  Michael J. Mantor ,  Radhakrishna Giduthuri ,  Eric J. Finger ,  Brian D. Emberling

IPC: G06F9/30 ,  G06F7/483

Abstract: Systems, apparatuses, and methods for routing traffic between clients and system memory are disclosed. A computing system includes a processor capable of executing single precision mathematical instructions on data sizes of M bits and half precision mathematical instructions on data sizes of N bits, which is less than M bits. At least two source operands with M bits indicated by a received instruction are read from a register file. If the instruction is a packed math instruction, at least a first source operand with a size of N bits less than M bits is selected from either a high portion or a low portion of one of the at least two source operands read from the register file. The instruction includes fields storing bits, each bit indicating the high portion or the low portion of a given source operand associated with a register identifier specified elsewhere in the instruction.

公开(公告)号：US10664285B1

公开(公告)日：2020-05-26

申请号：US16226411

申请日：2018-12-19

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Michael John Bedy ,  Eric J. Finger

IPC: G06F9/38 ,  G06F9/50 ,  G06F9/48

Abstract: A method of deriving intended thread data exchange patterns from source code includes identifying, based on a constant array, a pattern of data exchange between a plurality of threads in a wavefront. The constant array includes an array of source lane values identifying a thread location within the wavefront to read from for performing the pattern of data exchange. The pattern of data exchange is identified as a hardware-accelerated exchange pattern based on the constant array.

公开(公告)号：US11880683B2

公开(公告)日：2024-01-23

申请号：US15799560

申请日：2017-10-31

Applicant: Advanced Micro Devices, Inc.

Inventor： Jiasheng Chen ,  Bin He ,  Yunxiao Zou ,  Michael J. Mantor ,  Radhakrishna Giduthuri ,  Eric J. Finger ,  Brian D. Emberling

IPC: G06F9/30 ,  G06F7/483 ,  G06F7/57

CPC classification number: G06F9/30014 ,  G06F7/483 ,  G06F7/57 ,  G06F9/30036 ,  G06F9/30112 ,  G06F2207/3812 ,  G06F2207/3828

Abstract: Systems, apparatuses, and methods for efficiently processing arithmetic operations are disclosed. A computing system includes a processor capable of executing single precision mathematical instructions on data sizes of M bits and half precision mathematical instructions on data sizes of N bits, which is less than M bits. At least two source operands with M bits indicated by a received instruction are read from a register file. If the instruction is a packed math instruction, at least a first source operand with a size of N bits less than M bits is selected from either a high portion or a low portion of one of the at least two source operands read from the register file. The instruction includes fields storing bits, each bit indicating the high portion or the low portion of a given source operand associated with a register identifier specified elsewhere in the instruction.