公开(公告)号：US20140181384A1

公开(公告)日：2014-06-26

申请号：US13725024

申请日：2012-12-21

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Gabriel LOH ,  Jaewoong Sim

IPC: G11C7/10

CPC classification number: G06F12/00 ,  G06F12/0846 ,  G06F12/0882 ,  G06F12/0888 ,  G06F12/0893 ,  Y02D10/13

Abstract: A system, method and computer program product to store tag blocks in a tag buffer in order to provide early row-buffer miss detection, early page closing, and reductions in tag block transfers. A system comprises a tag buffer, a request buffer, and a memory controller. The request buffer stores a memory request having an associated tag. The memory controller compares the associated tag to a plurality of tags stored in the tag buffer and issues the memory request stored in the request buffer to either a memory cache or a main memory based on the comparison.

Abstract translation: 一种用于将标签块存储在标签缓冲器中的系统，方法和计算机程序产品，以便提供早期行缓冲器未命中检测，早期关闭和减少标签块传输。 系统包括标签缓冲器，请求缓冲器和存储器控制器。 请求缓冲器存储具有关联标签的存储器请求。 存储器控制器将相关联的标签与存储在标签缓冲器中的多个标签进行比较，并且基于该比较将存储在请求缓冲器中的存储器请求发布到存储器高速缓存或主存储器。

公开(公告)号：US20140122801A1

公开(公告)日：2014-05-01

申请号：US13663335

申请日：2012-10-29

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Gabriel LOH ,  James O'CONNOR

IPC: G06F12/14 ,  G06F12/08

CPC classification number: G06F11/3433 ,  G06F11/349 ,  G06F13/1663 ,  G06F2201/86 ,  G06F2201/88

Abstract: Embodiments are described for a method for controlling access to memory in a processor-based system comprising monitoring a number of interference events, such as bank contentions, bus contentions, row-buffer conflicts, and increased write-to-read turnaround time caused by a first core in the processor-based system that causes a delay in access to the memory by a second core in the processor-based system; deriving a control signal based on the number of interference events; and transmitting the control signal to one or more resources of the processor-based system to reduce the number of interference events from an original number of interference events.

Abstract translation: 描述了用于在基于处理器的系统中控制对存储器的访问的方法的实施例，包括监视多个干扰事件，例如银行争用，总线争用，行缓冲器冲突以及由 基于处理器的系统中的第一核心，其导致在基于处理器的系统中由第二核心访问存储器的延迟; 基于干扰事件的数量导出控制信号; 以及将所述控制信号发送到所述基于处理器的系统的一个或多个资源，以从原始数量的干扰事件减少干扰事件的数量。

公开(公告)号：US20250157987A1

公开(公告)日：2025-05-15

申请号：US18509410

申请日：2023-11-15

Applicant: Advanced Micro Devices, Inc.

Inventor： Gabriel LOH

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/367 ,  H01L23/48 ,  H01L23/498 ,  H01L25/18

Abstract: Memory layers and a digital device layer are configured into a three-dimensional integrated circuit (IC) die stack. The digital device layer has a first surface (side) located closest to a cooling solution and the memory layers are located on a second surface (side) of the digital device layer opposite to the first surface (side) thereof. The cooling solution is adapted to receive and dissipate heat from the digital device layer and the memory layers. Through-silicon vias (TSV) running through the memory layers and to the digital device layer are used to interconnect the signal, control and power supply voltages to circuits in these layers. Some of the TSVs are used to couple to external connections of a memory stack device. The digital device layer may be a complex electronic device layer such as a microprocessor or microcontroller for improved high speed signal transfers.

公开(公告)号：US20250125220A1

公开(公告)日：2025-04-17

申请号：US18379133

申请日：2023-10-11

Applicant: Advanced Micro Devices, Inc.

Inventor： Gabriel LOH ,  Divya Madapusi Srinivas PRASAD ,  Girish Anant KINI

IPC: H01L23/427 ,  H01L25/065 ,  H10B80/00

Abstract: An integrated circuit die stack is disclosed that includes a digital device layer, an underlying layer, and a cooling solution. The underlying layer has a lower power consumption relative to the digital device layer. The digital device layer is disposed closer to the cooling solution. In another example, memory layers and a digital device layer are configured into a three-dimensional memory stack. The digital device layer has a first surface (side) located closest to a cooling solution and the memory layers are located on a second surface (side) of the digital device layer opposite to the first surface (side) thereof. The cooling solution is adapted to receive and dissipate heat from the digital device layer and the memory layers.