公开(公告)号：US11567557B2

公开(公告)日：2023-01-31

申请号：US16729805

申请日：2019-12-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Sridhar Varadharajulu Gada ,  Sonu Arora ,  Xiaojie He

IPC: G06F1/00 ,  G06F1/3234 ,  G06F1/3296 ,  G06F1/3287 ,  G05F1/46

Abstract: An electronic device has a memory functional block that includes memory circuits and a memory physical layer (PHY) functional block with core logic that controls operations in the memory functional block, a memory PHY voltage regulator, a system voltage regulator, and a controller. The electronic device also includes a switch having an input coupled to an output of the memory PHY voltage regulator, another input coupled to an output of the system voltage regulator, and an output coupled to a power supply input of the core logic. The controller sets the switch so that electrical power is provided from the memory PHY voltage regulator to the core logic in a full power operating state. The controller sets the switch so that electrical power is provided from the system voltage regulator to the core logic in one or more low power operating states.

公开(公告)号：US11003588B2

公开(公告)日：2021-05-11

申请号：US16548692

申请日：2019-08-22

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： Sonu Arora ,  Paul Blinzer ,  Philip Ng ,  Nippon Harshadk Raval

IPC: G06F3/06 ,  G06F12/1027 ,  G06F13/16

Abstract: A networked input/output memory management unit (IOMMU) includes a plurality of IOMMUs. The networked IOMMU receives a memory access request that includes a domain physical address generated by a first address translation layer. The networked IOMMU selectively translates the domain physical address into a physical address in a system memory using one of the plurality of IOMMUs that is selected based on a type of a device that generated the memory access request. In some cases, the networked IOMMU is connected to a graphics processing unit (GPU), at least one peripheral device, and the memory. The networked IOMMU includes a command queue to receive the memory access requests, a primary IOMMU to selectively translate the domain physical address in memory access requests from the GPU, and a secondary IOMMU to translate the domain physical address in memory requests from the peripheral device.

公开(公告)号：US20190033939A1

公开(公告)日：2019-01-31

申请号：US15663464

申请日：2017-07-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Sonu Arora ,  Alexander Branover ,  Benjamin Tsien

IPC: G06F1/26 ,  G06F13/16

CPC classification number: G06F1/266 ,  G06F1/189 ,  G06F1/26 ,  G06F13/1673

Abstract: A data processing system includes a power manager for providing a power event depth signal in response to a power event request signal. A plurality of real-time clients is coupled to the power manager. Each real-time client includes a client buffer that has a plurality of entries for storing data. The real-time client also includes a register for storing a watermark threshold for the client buffer, as well as logic for providing an allow signal when a number of valid entries in the client buffer exceeds the watermark threshold. A power management state machine is coupled to each of the plurality of real-time clients. The power management state machine provides a power event start signal in response to all of the plurality of real-time clients providing respective allow signals.

公开(公告)号：US20250036467A1

公开(公告)日：2025-01-30

申请号：US18745744

申请日：2024-06-17

Applicant: Advanced Micro Devices, Inc.

Inventor： Sonu Arora ,  Daniel L. Bouvier

IPC: G06F9/50 ,  G06F1/3234 ,  G06F9/4401 ,  G06F12/02 ,  G06F12/1009 ,  G11C11/406 ,  G11C11/4074

Abstract: A method of operating a computing system includes storing a memory map identifying a first physical memory address as associated with a high performance memory and identifying a second physical memory address as associated with a low power consumption memory, servicing a first memory access request received from an application by accessing application data at the first physical memory address, in response to a change in one or more operating conditions of the computing system, moving the application data between the first physical memory address and the second physical memory address based on the memory map, and servicing a second memory access request received from the application by accessing the application data at the second physical memory address.

公开(公告)号：US12014213B2

公开(公告)日：2024-06-18

申请号：US16564388

申请日：2019-09-09

Applicant: Advanced Micro Devices, Inc.

Inventor： Sonu Arora ,  Daniel L. Bouvier

IPC: G06F9/50 ,  G06F1/3234 ,  G06F9/4401 ,  G06F12/02 ,  G06F12/1009 ,  G11C11/406 ,  G11C11/4074

CPC classification number: G06F9/5016 ,  G06F1/3275 ,  G06F9/4418 ,  G06F9/442 ,  G06F12/0238 ,  G06F12/1009 ,  G11C11/406 ,  G11C11/4074 ,  G06F2212/657

Abstract: A method of operating a computing system includes storing a memory map identifying a first physical memory address as associated with a high performance memory and identifying a second physical memory address as associated with a low power consumption memory, servicing a first memory access request received from an application by accessing application data at the first physical memory address, in response to a change in one or more operating conditions of the computing system, moving the application data between the first physical memory address and the second physical memory address based on the memory map, and servicing a second memory access request received from the application by accessing the application data at the second physical memory address.

公开(公告)号：US10775876B2

公开(公告)日：2020-09-15

申请号：US15858138

申请日：2017-12-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Thomas J. Gibney ,  Sonu Arora

IPC: G06F1/00 ,  G06F1/3296 ,  G06F1/28 ,  G06F1/3206 ,  G06F1/324

Abstract: A method and apparatus control power consumption of at least one functional unit on an integrated circuit by determining that a change in a first performance state is required for the at least one functional unit, and changing the first performance state to a second performance state that sets voltage for the functional unit to be at an under-voltage margin setting with respect to a nominal product minimum voltage of the functional unit.

公开(公告)号：US10474211B2

公开(公告)日：2019-11-12

申请号：US15663464

申请日：2017-07-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Sonu Arora ,  Alexander Branover ,  Benjamin Tsien

IPC: G06F1/00 ,  G06F1/26 ,  G06F13/16

Abstract: A data processing system includes a power manager for providing a power event depth signal in response to a power event request signal. A plurality of real-time clients is coupled to the power manager. Each real-time client includes a client buffer that has a plurality of entries for storing data. The real-time client also includes a register for storing a watermark threshold for the client buffer, as well as logic for providing an allow signal when a number of valid entries in the client buffer exceeds the watermark threshold. A power management state machine is coupled to each of the plurality of real-time clients. The power management state machine provides a power event start signal in response to all of the plurality of real-time clients providing respective allow signals.

公开(公告)号：US11513973B2

公开(公告)日：2022-11-29

申请号：US16723185

申请日：2019-12-20

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Sonu Arora ,  Benjamin Tsien ,  Alexander J. Branover

IPC: G06F12/14 ,  G06F12/06 ,  G06F12/0877 ,  G06F9/54 ,  G06F12/1027 ,  G06F9/50 ,  G06F11/30 ,  G06F12/1009 ,  G06F9/30

Abstract: A processor in a system is responsive to a coherent memory request buffer having a plurality of entries to store coherent memory requests from a client module and a non-coherent memory request buffer having a plurality of entries to store non-coherent memory requests from the client module. The client module buffers coherent and non-coherent memory requests and releases the memory requests based on one or more conditions of the processor or one of its caches. The memory requests are released to a central data fabric and into the system based on a first watermark associated with the coherent memory buffer and a second watermark associated with the non-coherent memory buffer.

公开(公告)号：US20210200297A1

公开(公告)日：2021-07-01

申请号：US16729805

申请日：2019-12-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Sridhar Varadharajulu Gada ,  Sonu Arora ,  Xiaojie He

IPC: G06F1/3234 ,  G06F1/3287 ,  G06F1/3296

Abstract: An electronic device has a memory functional block that includes memory circuits and a memory physical layer (PHY) functional block with core logic that controls operations in the memory functional block, a memory PHY voltage regulator, a system voltage regulator, and a controller. The electronic device also includes a switch having an input coupled to an output of the memory PHY voltage regulator, another input coupled to an output of the system voltage regulator, and an output coupled to a power supply input of the core logic. The controller sets the switch so that electrical power is provided from the memory PHY voltage regulator to the core logic in a full power operating state. The controller sets the switch so that electrical power is provided from the system voltage regulator to the core logic in one or more low power operating states.

公开(公告)号：US10572183B2

公开(公告)日：2020-02-25

申请号：US15787459

申请日：2017-10-18

Applicant: Advanced Micro Devices, Inc.

Inventor： Sonu Arora ,  Guhan Krishnan ,  Kevin Brandl

IPC: G06F12/00 ,  G06F13/00 ,  G06F3/06

Abstract: A data processing system includes a memory and a data processor. The data processor is connected to the memory and adapted to access the memory in response to scheduled memory access requests. The data processor has power management logic that, in response to detecting a memory power state change, determines whether to retrain or suppress retraining of at least one parameter related to accessing the memory based on an operating state of the memory. The power management logic further determines a retraining interval for retraining the at least one parameter related to accessing the memory, and initiates a retraining operation in response to the memory power state change based on the operating state of the memory being outside of a predetermined threshold.