公开(公告)号：US6363022B2

公开(公告)日：2002-03-26

申请号：US92235101

申请日：2001-08-02

Applicant: ADVANTEST CORP

Inventor： TSUTO MASARU

IPC: G01R31/28 ,  G06F12/16 ,  G11C29/10 ,  G11C29/56 ,  G11C7/00

CPC classification number: G11C29/56 ,  G11C29/10

Abstract: A pattern generator generates parallel pattern data and applies it to packet generating parts provided corresponding to row-address and column-address pins of a memory device under test. The pattern generator contains a packet select signal generating part that generates two packet select signals for generating respective cycle numbers in a sequence of cycles in an arbitrary packet period. In data setting parts provided corresponding to the row-address and column-address pins, respectively, bit positions of the data to be fed to the corresponding pins in the parallel pattern data are prestored in correspondence with the cycle numbers. In each cycle the bit positions corresponding to the cycle number are read out by the packet select signals corresponding to the row-address and column-address pins, and in the corresponding packet generating parts data bits corresponding to their bit positions in the parallel pattern data are selected and provided to the corresponding pins.

Abstract translation: 模式发生器产生并行模式数据并将其应用于与被测存储器件的行地址和列地址引脚相对应地提供的分组生成部分。 图案生成器包括分组选择信号生成部，其生成两个分组选择信号，用于在任意分组周期中以循环周期生成各个周期数。 在与行地址和列地址引脚相对应地设置的数据设置部分中，分别将要馈送到并行模式数据中的相应引脚的数据的位位置与循环数相对应地预存。 在每个周期中，对应于循环编号的位位置由对应于行地址和列地址引脚的分组选择信号读出，并且在对应的分组生成部分中，对应于它们在并行模式数据中的位位置的数据位 被选择并提供给相应的引脚。