公开(公告)号：US20170353335A1

公开(公告)日：2017-12-07

申请号：US15684310

申请日：2017-08-23

Applicant: ALTERA CORPORATION

Inventor： David W. MENDEL ,  Han Hua LEONG

IPC: H04L25/14 ,  H04L12/24 ,  H04L12/26 ,  H04L12/875

CPC classification number: H04L25/14 ,  G06F5/06 ,  H04L41/0896 ,  H04L43/087 ,  H04L47/56

Abstract: Circuits and methods are disclosed for low-skew bonding of a plurality of data channels into a multi-lane data channel. In one embodiment, phase-measuring first-in first-out buffer circuits buffer pre-buffer parallel data signals and generate phase-measurement signals. A channel-bonding control circuit receives the phase-measurement signals and generates bit-slip control signals. Transmission bit-slip circuits slip integer numbers of bits based on the bit-slip control signals. Bypass registers may be used when the integer number of bits is greater or equal to the parallel width of a lane. In another embodiment, the channel-bonding control circuit receives the phase-measurement signals from the phase-measuring FIFO buffer circuits and generates clock-slip control signals. Clock slip circuits controllably slip parallel clock signals by integer numbers of unit intervals of a serial clock signal. Various other aspects, features, and embodiments are also disclosed.