公开(公告)号：US09948307B2

公开(公告)日：2018-04-17

申请号：US15633473

申请日：2017-06-26

Applicant: Altera Corporation

Inventor： Navid Azizi ,  Gordon Raymond Chiu ,  Michael Howard Kipper

IPC: H03K19/20 ,  G06F17/50

CPC classification number: H03K19/20 ,  G06F17/50 ,  G06F17/5045 ,  H03K19/018507

Abstract: Techniques and mechanisms allow a Programmable Logic Device (PLD) to support a pseudo open drain (POD) input/output (I/O) standard used in interface protocols such as fourth generation double data rate (DDR4). An OR gate with inputs including data and an inverted output enable from a user's design may be inserted into programmable logic. The output of the OR gate may be coupled with an input of an I/O buffer.

公开(公告)号：US20170359073A1

公开(公告)日：2017-12-14

申请号：US15633473

申请日：2017-06-26

Applicant: Altera Corporation

Inventor： Navid Azizi ,  Gordon Raymond Chiu ,  Michael Howard Kipper

IPC: H03K19/20 ,  G06F17/50

CPC classification number: H03K19/20 ,  G06F17/50 ,  G06F17/5045 ,  H03K19/018507

Abstract: Techniques and mechanisms allow a Programmable Logic Device (PLD) to support a pseudo open drain (POD) input/output (I/O) standard used in interface protocols such as fourth generation double data rate (DDR4). An OR gate with inputs including data and an inverted output enable from a user's design may be inserted into programmable logic. The output of the OR gate may be coupled with an input of an I/O buffer.

公开(公告)号：US09698795B1

公开(公告)日：2017-07-04

申请号：US13935273

申请日：2013-07-03

Applicant: Altera Corporation

Inventor： Navid Azizi ,  Gordon Raymond Chiu ,  Michael Howard Kipper

IPC: H03K19/20 ,  G06F17/50

CPC classification number: H03K19/20 ,  G06F17/50 ,  G06F17/5045 ,  H03K19/018507

Abstract: Techniques and mechanisms allow a Programmable Logic Device (PLD) to support a pseudo open drain (POD) input/output (I/O) standard used in interface protocols such as fourth generation double data rate (DDR4). An OR gate with inputs including data and an inverted output enable from a user's design may be inserted into programmable logic. The output of the OR gate may be coupled with an input of an I/O buffer.