公开(公告)号：US09876007B1

公开(公告)日：2018-01-23

申请号：US15149244

申请日：2016-05-09

Applicant: APPLIED MICRO CIRCUITS CORPORATION

Inventor： Ronen Cohen ,  Alfred Yeung ,  Ojas Dharia

IPC: H01L21/8242 ,  H01L27/02 ,  H01L49/02 ,  H01L23/522 ,  H01L23/535 ,  G06F17/50

CPC classification number: H01L27/0288 ,  G06F17/5072 ,  G06F17/5077 ,  G06F17/5081 ,  H01L23/5223 ,  H01L23/535 ,  H01L27/0207 ,  H01L28/60

Abstract: A metal-insulator-metal (MIM) capacitor design methodology and system substantially maximizes the benefits of including MIM capacitors in an integrated circuit design while substantially minimizing the negative impacts resulting from increased capacitance. A process analysis is performed on an integrated circuit design to determine a metal layer that is likely to be most adversely affected by the presence of MIM capacitor cells. The MIM capacitor cells are then designed to have specific sizes and orientations based on results of the process analysis, taking the most affected metal layer into consideration. Finally, the MIM capacitor cells are placed at selected locations on the die in an algorithmic fashion in order to satisfy a design target of maximizing coverage area while avoiding interference with signal paths and critical or sensitive components.

公开(公告)号：US20170261537A1

公开(公告)日：2017-09-14

申请号：US15068737

申请日：2016-03-14

Applicant: APPLIED MICRO CIRCUITS CORPORATION

Inventor： Yan Chong ,  Luca Ravezzi ,  Alfred Yeung ,  Hamid Partovi

IPC: G01R19/165 ,  G01R17/02 ,  G01R19/00

CPC classification number: G01R19/16504 ,  G01R17/02 ,  G01R19/0084 ,  G01R31/2884 ,  G01R31/3004 ,  G06F1/305

Abstract: A self-referenced on-die voltage droop detector generates a reference voltage from the supply voltage of an integrated circuit's power distribution network, and compares this reference voltage to the transient supply voltage in order to detect voltage droops. The detector responds to detected occurrences of voltage droop with low latency by virtue of being located on-die. Also, by generating the reference voltage from the integrated circuit's power domain rather than using a separate reference voltage source, the detector does not introduce noise and distortion associated with a separate power domain.

公开(公告)号：US20170063355A1

公开(公告)日：2017-03-02

申请号：US14838778

申请日：2015-08-28

Applicant: APPLIED MICRO CIRCUITS CORPORATION

Inventor： Rich Thaik ,  Alfred Yeung ,  April Lambert ,  Jeremy Plunkett

IPC: H03K5/1252 ,  H01L23/522 ,  H01L23/525

CPC classification number: H03K5/1252 ,  H01L23/50 ,  H01L23/5223 ,  H01L23/525

Abstract: A semiconductor chip allows for a selected amount of on-die decoupling capacitance to be connected to a very-large-scale integrated circuit (VLSI) system after the circuit design is complete. The semiconductor chip comprises an integrated circuit disposed on a packaging substrate, and a power distribution network that is electrically connectable to the integrated circuit via a programmable connectivity array via the packaging substrate.

Abstract translation: 在电路设计完成之后，半导体芯片允许选定数量的管芯上的去耦电容连接到大规模集成电路（VLSI）系统。 半导体芯片包括设置在封装基板上的集成电路，以及经由可编程连接阵列经由封装基板与集成电路电连接的配电网。

公开(公告)号：US09438225B1

公开(公告)日：2016-09-06

申请号：US14736882

申请日：2015-06-11

Applicant: APPLIED MICRO CIRCUITS CORPORATION

Inventor： Alfred Yeung ,  Ronen Cohan

IPC: H03K17/16

CPC classification number: H01L27/0248

Abstract: A decoupling capacitor circuit design facilitates high operational frequency without sacrificing area efficiency. In order to disassociate the sometimes opposing design criteria of high operational frequency and area efficiency, a p-channel field effect transistor (PFET) and an n-channel field effect transistor are connected in a half-cross-coupled (HCC) fashion. The HCC circuit is then supplemented by at least one area efficient capacitance (AEC) device. The half-cross-coupled transistors address the high frequency design requirement, while the AEC device(s) address the high area efficiency requirement. The design eliminates the undesirable trade-off between operating frequency and area efficiency inherent in some conventional DCAP designs.

Abstract translation: 去耦电容电路设计有助于高工作频率，而不牺牲面积效率。 为了解决高操作频率和面积效率的有时相反的设计标准，p沟道场效应晶体管（PFET）和n沟道场效应晶体管以半交叉耦合（HCC）方式连接。 然后，HCC电路由至少一个区域有效电容（AEC）装置补充。 半交叉耦合晶体管满足高频设计要求，而AEC器件满足高区域效率要求。 该设计消除了一些常规DCAP设计中固有的工作频率和面积效率之间的不利权衡。