公开(公告)号：US09876007B1

公开(公告)日：2018-01-23

申请号：US15149244

申请日：2016-05-09

Applicant: APPLIED MICRO CIRCUITS CORPORATION

Inventor： Ronen Cohen ,  Alfred Yeung ,  Ojas Dharia

IPC: H01L21/8242 ,  H01L27/02 ,  H01L49/02 ,  H01L23/522 ,  H01L23/535 ,  G06F17/50

CPC classification number: H01L27/0288 ,  G06F17/5072 ,  G06F17/5077 ,  G06F17/5081 ,  H01L23/5223 ,  H01L23/535 ,  H01L27/0207 ,  H01L28/60

Abstract: A metal-insulator-metal (MIM) capacitor design methodology and system substantially maximizes the benefits of including MIM capacitors in an integrated circuit design while substantially minimizing the negative impacts resulting from increased capacitance. A process analysis is performed on an integrated circuit design to determine a metal layer that is likely to be most adversely affected by the presence of MIM capacitor cells. The MIM capacitor cells are then designed to have specific sizes and orientations based on results of the process analysis, taking the most affected metal layer into consideration. Finally, the MIM capacitor cells are placed at selected locations on the die in an algorithmic fashion in order to satisfy a design target of maximizing coverage area while avoiding interference with signal paths and critical or sensitive components.