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    Dual vector arithmetic logic unit
    4.
    发明授权
    Dual vector arithmetic logic unit 有权

    公开(公告)号：US11675568B2

    公开(公告)日：2023-06-13

    申请号：US17121354

    申请日：2020-12-14

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： Bin He ,  Brian Emberling ,  Mark Leather ,  Michael Mantor

    IPC: G06F7/57 ,  G06F17/16 ,  G06T1/20 ,  G06F9/38 ,  G06F15/80

    CPC classification number: G06F7/57 ,  G06F9/3867 ,  G06F17/16 ,  G06T1/20 ,  G06F15/8015

    Abstract: A processing system executes wavefronts at multiple arithmetic logic unit (ALU) pipelines of a single instruction multiple data (SIMD) unit in a single execution cycle. The ALU pipelines each include a number of ALUs that execute instructions on wavefront operands that are collected from vector general process register (VGPR) banks at a cache and output results of the instructions executed on the wavefronts at a buffer. By storing wavefronts supplied by the VGPR banks at the cache, a greater number of wavefronts can be made available to the SIMD unit without increasing the VGPR bandwidth, enabling multiple ALU pipelines to execute instructions during a single execution cycle.

    Dual vector arithmetic logic unit
    6.
    发明授权
    Dual vector arithmetic logic unit 有权

    公开(公告)号：US12299413B2

    公开(公告)日：2025-05-13

    申请号：US18414164

    申请日：2024-01-16

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： Bin He ,  Brian Emberling ,  Mark Leather ,  Michael Mantor

    IPC: G06F7/57 ,  G06F9/38 ,  G06F17/16 ,  G06T1/20 ,  G06F15/80

    Abstract: A processing system executes wavefronts at multiple arithmetic logic unit (ALU) pipelines of a single instruction multiple data (SIMD) unit in a single execution cycle. The ALU pipelines each include a number of ALUs that execute instructions on wavefront operands that are collected from vector general process register (VGPR) banks at a cache and output results of the instructions executed on the wavefronts at a buffer. By storing wavefronts supplied by the VGPR banks at the cache, a greater number of wavefronts can be made available to the SIMD unit without increasing the VGPR bandwidth, enabling multiple ALU pipelines to execute instructions during a single execution cycle.

    Software-based instruction scoreboard for arithmetic logic units
    7.
    发明授权
    Software-based instruction scoreboard for arithmetic logic units 有权

    公开(公告)号：US11847462B2

    公开(公告)日：2023-12-19

    申请号：US17122089

    申请日：2020-12-15

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： Brian Emberling

    IPC: G06F9/38 ,  G06F7/57

    CPC classification number: G06F9/3838 ,  G06F7/57

    Abstract: A software-based instruction scoreboard indicates dependencies between closely-issued instructions issued to an arithmetic logic unit (ALU) pipeline. The software-based instruction scoreboard inserts one or more control words into the command stream between the dependent instructions, which is then executed by the ALU pipeline. The control words identify the instruction(s) upon which the dependent instructions depend (parent instructions) so that the GPU hardware can ensure that the ALU pipeline does not stall while the dependent instruction waits for results from the parent instruction.

    Exception handler for sampling draw dispatch identifiers
    8.
    发明授权
    Exception handler for sampling draw dispatch identifiers 有权

    公开(公告)号：US11386518B2

    公开(公告)日：2022-07-12

    申请号：US16580654

    申请日：2019-09-24

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： Michael Mantor ,  Alexander Fuad Ashkar ,  Randy Ramsey ,  Mangesh P. Nijasure ,  Brian Emberling

    IPC: G06T15/00 ,  G06T1/20 ,  G06F9/38 ,  G06T15/80

    Abstract: The address of the draw or dispatch packet responsible for creating an exception is tied to a shader/wavefront back to the draw command from which it originated. In various embodiments, a method of operating a graphics pipeline and exception handling includes receiving, at a command processor of a graphics processing unit (GPU), an exception signal indicating an occurrence of a pipeline exception at a shader stage of a graphics pipeline. The shader stage generates an exception signal in response to a pipeline exception and transmits the exception signal to the command processor. The command processor determines, based on the exception signal, an address of a command packet responsible for the occurrence of the pipeline exception.

    CONVOLUTIONAL NEURAL NETWORK OPERATIONS
    10.
    发明申请
    CONVOLUTIONAL NEURAL NETWORK OPERATIONS 有权

    公开(公告)号：US20230097279A1

    公开(公告)日：2023-03-30

    申请号：US17489734

    申请日：2021-09-29

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Brian Emberling ,  Michael Mantor ,  Michael Y. Chow ,  Bin He

    IPC: G06N3/04 ,  G06F9/38 ,  G06F17/16

    Abstract: Methods and systems are disclosed for executing operations on single-instruction-multiple-data (SIMD) units. Techniques disclosed perform a dot product operation on input data during one computer cycle, including convolving the input data, generating intermediate data, and applying one or more transitional operations to the intermediate data to generate output data. Aspects described, wherein the input data is an input to a layer of a convolutional neural network and the generated output data is the output of the layer.

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