公开(公告)号：US20230071807A1

公开(公告)日：2023-03-09

申请号：US17984796

申请日：2022-11-10

Applicant: Advanced Micro Devices, Inc.

Inventor： Russell J. Schreiber ,  Ryan T. Freese ,  Eric W. Busta

IPC: G11C7/06

Abstract: A sense amplifier is biased to reduce leakage current equalize matched transistor bias during an idle state. A first read select transistor couples a true bit line and a sense amplifier true (SAT) signal line and a second read select transistor couples a complement bit line and a sense amplifier complement (SAC) signal line. The SAT and SAC signal lines are precharged during a precharge state. An equalization circuit shorts the SAT and SAC signal lines during the precharge state. A differential sense amplifier circuit for latching the memory cell value is coupled to the SAT signal line and the SAC signal line. The precharge circuit and the differential sense amplifier circuit are turned off during a sleep state to cause the SAT and SAC signal lines to float. A sleep circuit shorts the SAT and SAC signal lines during the sleep state.

公开(公告)号：US20220208234A1

公开(公告)日：2022-06-30

申请号：US17133956

申请日：2020-12-24

Applicant: Advanced Micro Devices, Inc.

Inventor： Russell J. Schreiber ,  Ryan T. Freese ,  Eric W. Busta

IPC: G11C7/06

Abstract: A sense amplifier is biased to reduce leakage current equalize matched transistor bias during an idle state. A first read select transistor couples a true bit line and a sense amplifier true (SAT) signal line and a second read select transistor couples a complement bit line and a sense amplifier complement (SAC) signal line. The SAT and SAC signal lines are precharged during a precharge state. An equalization circuit shorts the SAT and SAC signal lines during the precharge state. A differential sense amplifier circuit for latching the memory cell value is coupled to the SAT signal line and the SAC signal line. The precharge circuit and the differential sense amplifier circuit are turned off during a sleep state to cause the SAT and SAC signal lines to float. A sleep circuit shorts the SAT and SAC signal lines during the sleep state.

公开(公告)号：US11854652B2

公开(公告)日：2023-12-26

申请号：US17984796

申请日：2022-11-10

Applicant: Advanced Micro Devices, Inc.

Inventor： Russell J. Schreiber ,  Ryan T. Freese ,  Eric W. Busta

IPC: G11C7/06

CPC classification number: G11C7/065

Abstract: A sense amplifier is biased to reduce leakage current equalize matched transistor bias during an idle state. A first read select transistor couples a true bit line and a sense amplifier true (SAT) signal line and a second read select transistor couples a complement bit line and a sense amplifier complement (SAC) signal line. The SAT and SAC signal lines are precharged during a precharge state. An equalization circuit shorts the SAT and SAC signal lines during the precharge state. A differential sense amplifier circuit for latching the memory cell value is coupled to the SAT signal line and the SAC signal line. The precharge circuit and the differential sense amplifier circuit are turned off during a sleep state to cause the SAT and SAC signal lines to float. A sleep circuit shorts the SAT and SAC signal lines during the sleep state.

公开(公告)号：US20150006810A1

公开(公告)日：2015-01-01

申请号：US13929040

申请日：2013-06-27

Applicant: Advanced Micro Devices, Inc.

Inventor： Eric W. Busta ,  Karthik Natarajan ,  Brian M. Lay ,  Gregory A. Constant

IPC: G11C7/10

CPC classification number: G11C8/16 ,  G06F9/3012 ,  G11C7/1075 ,  G11C2207/007

Abstract: A register file includes a substrate, a plurality of entries, and a plurality of read ports. Each entry includes a corresponding subset of a plurality of memory cells defined on the substrate. Each read port includes a plurality of access elements defined on the substrate. Each access element is associated with a particular common bit position of each of the entries. A plurality of entry access groups are disposed in adjacent columns on the substrate. Each entry access group is associated with a corresponding one of the plurality of entries and includes the access elements for all of the read ports for the corresponding entry.

Abstract translation: 寄存器文件包括基板，多个入口和多个读取端口。 每个条目包括限定在基板上的多个存储器单元的相应子集。 每个读取端口包括限定在基板上的多个访问元件。 每个访问元素与每个条目的特定公共位位置相关联。 多个入口访问组被布置在基板上的相邻列中。 每个条目访问组与多个条目中的相应一个条目相关联，并且包括用于相应条目的所有读取端口的访问元素。

公开(公告)号：US11514956B2

公开(公告)日：2022-11-29

申请号：US17133956

申请日：2020-12-24

Applicant: Advanced Micro Devices, Inc.

Inventor： Russell J. Schreiber ,  Ryan T. Freese ,  Eric W. Busta

IPC: G11C7/06

Abstract: A sense amplifier is biased to reduce leakage current equalize matched transistor bias during an idle state. A first read select transistor couples a true bit line and a sense amplifier true (SAT) signal line and a second read select transistor couples a complement bit line and a sense amplifier complement (SAC) signal line. The SAT and SAC signal lines are precharged during a precharge state. An equalization circuit shorts the SAT and SAC signal lines during the precharge state. A differential sense amplifier circuit for latching the memory cell value is coupled to the SAT signal line and the SAC signal line. The precharge circuit and the differential sense amplifier circuit are turned off during a sleep state to cause the SAT and SAC signal lines to float. A sleep circuit shorts the SAT and SAC signal lines during the sleep state.

公开(公告)号：US09779792B2

公开(公告)日：2017-10-03

申请号：US13929040

申请日：2013-06-27

Applicant: Advanced Micro Devices, Inc.

Inventor： Eric W. Busta ,  Karthik Natarajan ,  Brian M. Lay ,  Gregory A. Constant

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G11C8/16 ,  G06F9/30 ,  G11C7/10

CPC classification number: G11C8/16 ,  G06F9/3012 ,  G11C7/1075 ,  G11C2207/007

Abstract: A register file includes a substrate, a plurality of entries, and a plurality of read ports. Each entry includes a corresponding subset of a plurality of memory cells defined on the substrate. Each read port includes a plurality of access elements defined on the substrate. Each access element is associated with a particular common bit position of each of the entries. A plurality of entry access groups are disposed in adjacent columns on the substrate. Each entry access group is associated with a corresponding one of the plurality of entries and includes the access elements for all of the read ports for the corresponding entry.