公开(公告)号：US11675718B2

公开(公告)日：2023-06-13

申请号：US17214771

申请日：2021-03-26

Applicant: Advanced Micro Devices, Inc.

Inventor： Eric Christopher Morton ,  Pravesh Gupta ,  Bryan P Broussard ,  Li Ou

IPC: G06F13/24 ,  G06F9/48 ,  G06F9/30 ,  G06F13/42 ,  G06F13/26

CPC classification number: G06F13/24 ,  G06F9/30101 ,  G06F9/4812 ,  G06F9/4818 ,  G06F9/4831 ,  G06F13/26 ,  G06F13/4221

Abstract: A computing system may implement a low priority arbitration interrupt method that includes receiving a message signaled interrupt (MSI) message from an input output hub (I/O hub) transmitted over an interconnect fabric, selecting a processor to interrupt from a cluster of processors based on arbitration parameters, and communicating an interrupt service routine to the selected processor, wherein the I/O hub and the cluster of processors are located within a common domain.

公开(公告)号：US12045182B1

公开(公告)日：2024-07-23

申请号：US18298587

申请日：2023-04-11

Applicant: Advanced Micro Devices, Inc.

Inventor： Eric Christopher Morton ,  Pravesh Gupta ,  Bryan P Broussard ,  Li Ou

IPC: G06F13/24 ,  G06F9/30 ,  G06F9/48 ,  G06F13/26 ,  G06F13/42

CPC classification number: G06F13/24 ,  G06F9/30101 ,  G06F9/4812 ,  G06F9/4818 ,  G06F9/4831 ,  G06F13/26 ,  G06F13/4221

Abstract: A computing system may implement a low priority arbitration interrupt method that includes receiving a message signaled interrupt (MSI) message from an input output hub (I/O hub) transmitted over an interconnect fabric, selecting a processor to interrupt from a cluster of processors based on arbitration parameters, and communicating an interrupt service routine to the selected processor, wherein the I/O hub and the cluster of processors are located within a common domain.

公开(公告)号：US20220309013A1

公开(公告)日：2022-09-29

申请号：US17214771

申请日：2021-03-26

Applicant: Advanced Micro Devices, Inc.

Inventor： Eric Christopher Morton ,  Pravesh Gupta ,  Bryan P Broussard ,  Li Ou

IPC: G06F13/24 ,  G06F9/30 ,  G06F9/48 ,  G06F13/42

Abstract: A computing system may implement a low priority arbitration interrupt method that includes receiving a message signaled interrupt (MSI) message from an input output hub (I/O hub) transmitted over an interconnect fabric, selecting a processor to interrupt from a cluster of processors based on arbitration parameters, and communicating an interrupt service routine to the selected processor, wherein the I/O hub and the cluster of processors are located within a common domain.