公开(公告)号：US20180349057A1

公开(公告)日：2018-12-06

申请号：US16055716

申请日：2018-08-06

Applicant: ATI Technologies ULC ,  ADVANCED MICRO DEVICES, INC.

Inventor： Nima OSQUEIZADEH ,  Paul BLINZER

IPC: G06F3/06

CPC classification number: G06F3/0611 ,  G06F3/0635 ,  G06F3/0658 ,  G06F3/068 ,  G06F3/0685

Abstract: Described herein is a method and system for directly accessing and transferring data between a first memory architecture and a second memory architecture associated with a graphics processing unit (GPU) by treating the first memory architecture, the second memory architecture and system memory as a single physical memory, where the first memory architecture is a non-volatile memory (NVM) and the second memory architecture is a local memory. Upon accessing a virtual address (VA) range by a processor, the requested content is paged in from the single physical memory and is then redirected by a virtual storage driver to the second memory architecture or the system memory, depending on which of the GPU or CPU triggered the access request. The memory transfer occurs without awareness of the application and the operating system.

公开(公告)号：US20210056042A1

公开(公告)日：2021-02-25

申请号：US16548692

申请日：2019-08-22

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： Sonu ARORA ,  Paul BLINZER ,  Philip NG ,  Nippon Harshadk RAVAL

IPC: G06F12/1027 ,  G06F13/16

Abstract: A networked input/output memory management unit (IOMMU) includes a plurality of IOMMUs. The networked IOMMU receives a memory access request that includes a domain physical address generated by a first address translation layer. The networked IOMMU selectively translates the domain physical address into a physical address in a system memory using one of the plurality of IOMMUs that is selected based on a type of a device that generated the memory access request. In some cases, the networked IOMMU is connected to a graphics processing unit (GPU), at least one peripheral device, and the memory. The networked IOMMU includes a command queue to receive the memory access requests, a primary IOMMU to selectively translate the domain physical address in memory access requests from the GPU, and a secondary IOMMU to translate the domain physical address in memory requests from the peripheral device.

公开(公告)号：US20240303113A1

公开(公告)日：2024-09-12

申请号：US18119234

申请日：2023-03-08

Applicant: Advanced Micro Devices, Inc.

Inventor： Anthony GUTIERREZ ,  Paul BLINZER ,  Samuel BAYLISS ,  Stephen Alexander ZEKANY ,  Ali Arda EKER

IPC: G06F9/48 ,  G06F9/38

CPC classification number: G06F9/4893 ,  G06F9/3838

Abstract: Embodiments herein describe a pull-based model to dispatch tasks in an accelerator device. That is, rather than a push-based model where a connected host pushes tasks into hardware (HW) queues in the accelerator device, the embodiments herein describe a pull-based model where a command processor (CP) loads tasks into the HW queues after any data dependencies have been resolved.