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    Allocation of memory buffers in computing system with multiple memory channels
    1.
    发明授权
    Allocation of memory buffers in computing system with multiple memory channels 有权

    公开(公告)号：US10795837B2

    公开(公告)日：2020-10-06

    申请号：US15958805

    申请日：2018-04-20

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Greg Sadowski ,  Philip J. Rogers

    IPC: G06F12/00 ,  G06F13/00 ,  G06F13/16

    Abstract: A method, computer program product, and system are provided for associating one or more memory buffers in a computing system with a plurality of memory channels. The method can include associating a first memory buffer to a first plurality of memory banks, where the first plurality of memory banks spans over a first set of one or more memory channels. Similarly, the method can include associating a second memory buffer to a second plurality of memory banks, where the second plurality of memory banks spans over a second set of one or more memory channels. The method can also include associating a first sequence identifier and a second sequence identifier with the first memory buffer and the second memory buffer, respectively. Further, the method can include accessing the first and second memory buffers based on the first and second sequence identifiers.

    Policies for shader resource allocation in a shader core
    3.
    发明授权
    Policies for shader resource allocation in a shader core 有权

    公开(公告)号：US10579388B2

    公开(公告)日：2020-03-03

    申请号：US16040224

    申请日：2018-07-19

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Robert Scott Hartog ,  Mark Leather ,  Michael Mantor ,  Rex McCrary ,  Sebastien Nussbaum ,  Philip J. Rogers ,  Ralph Clay Taylor ,  Thomas Woller

    IPC: G06F9/38 ,  G06F9/48 ,  G06T1/20

    Abstract: A method for use in a processor for arbitrating between multiple processes to select wavefronts for execution on a shader core is provided. The processor includes a compute pipeline configured to issue wavefronts to the shader core for execution, a hardware queue descriptor associated with the compute pipeline, and the shader core. The shader core is configured to execute work for the compute pipeline corresponding to a first memory queue descriptor executed using data for the first memory queue descriptor that is loaded into a first hardware queue descriptor. The processor is configured to detect a context switch condition, and, responsive to the context switch condition, perform a context switch operation including loading data for a second memory queue descriptor into the first hardware queue descriptor. The shader core is configured to execute work corresponding to the second memory queue descriptor that is loaded into the first hardware queue descriptor.

    SHARED VIRTUAL ADDRESS SPACE FOR HETEROGENEOUS PROCESSORS
    7.
    发明申请
    SHARED VIRTUAL ADDRESS SPACE FOR HETEROGENEOUS PROCESSORS 审中-公开
    用于异构处理器的共享虚拟地址空间

    公开(公告)号：US20160378674A1

    公开(公告)日：2016-12-29

    申请号：US14747944

    申请日：2015-06-23

    Applicant: ATI Technologies ULC ,  Advanced Micro Devices, Inc.

    Inventor： Gongxian Jeffrey Cheng ,  Mark Fowler ,  Philip J. Rogers ,  Benjamin T. Sander ,  Anthony Asaro ,  Mike Mantor ,  Raja Koduri

    IPC: G06F12/10

    CPC classification number: G06F12/1009 ,  G06F12/1072 ,  G06F12/1081 ,  G06F15/163 ,  G06F2212/1016 ,  G06F2212/151 ,  G06F2212/152 ,  G06F2212/251

    Abstract: A processor uses the same virtual address space for heterogeneous processing units of the processor. The processor employs different sets of page tables for different types of processing units, such as a CPU and a GPU, wherein a memory management unit uses each set of page tables to translate virtual addresses of the virtual address space to corresponding physical addresses of memory modules associated with the processor. As data is migrated between memory modules, the physical addresses in the page tables can be updated to reflect the physical location of the data for each processing unit.

    Abstract translation: 处理器对处理器的异构处理单元使用相同的虚拟地址空间。 处理器对不同类型的处理单元（例如CPU和GPU）采用不同的页表，其中存储器管理单元使用每组页表来将虚拟地址空间的虚拟地址转换为存储器模块的相应物理地址 与处理器相关联。 随着数据在内存模块之间迁移，可以更新页表中的物理地址，以反映每个处理单元的数据的物理位置。

    POLICIES FOR SHADER RESOURCE ALLOCATION IN A SHADER CORE
    9.
    发明申请
    POLICIES FOR SHADER RESOURCE ALLOCATION IN A SHADER CORE 审中-公开

    公开(公告)号：US20180321946A1

    公开(公告)日：2018-11-08

    申请号：US16040224

    申请日：2018-07-19

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Robert Scott Hartog ,  Mark Leather ,  Michael Mantor ,  Rex McCrary ,  Sebastien Nussbaum ,  Philip J. Rogers ,  Ralph Clay Taylor ,  Thomas Woller

    IPC: G06F9/38 ,  G06T1/20 ,  G06F9/48

    CPC classification number: G06F9/3851 ,  G06F9/3879 ,  G06F9/4881 ,  G06T1/20

    Abstract: A method for use in a processor for arbitrating between multiple processes to select wavefronts for execution on a shader core is provided. The processor includes a compute pipeline configured to issue wavefronts to the shader core for execution, a hardware queue descriptor associated with the compute pipeline, and the shader core. The shader core is configured to execute work for the compute pipeline corresponding to a first memory queue descriptor executed using data for the first memory queue descriptor that is loaded into a first hardware queue descriptor. The processor is configured to detect a context switch condition, and, responsive to the context switch condition, perform a context switch operation including loading data for a second memory queue descriptor into the first hardware queue descriptor. The shader core is configured to execute work corresponding to the second memory queue descriptor that is loaded into the first hardware queue descriptor.

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