公开(公告)号：US20170371653A1

公开(公告)日：2017-12-28

申请号：US15191374

申请日：2016-06-23

Applicant: Advanced Micro Devices, Inc.

Inventor： Robert A. Gottlieb ,  Christopher L. Reeve ,  Michael John Bedy

IPC: G06F9/30 ,  G06F15/80

CPC classification number: G06F9/3005 ,  G06F9/3012 ,  G06F15/8007

Abstract: A method and apparatus for scheduling instructions of a shader program for a graphics processing unit (GPU) with a fixed number of registers. The method and apparatus include computing, via a processing unit (PU), a liveness-based register usage across all basic blocks in the shader program, computing, via the PU, the range of numbers of waves of a plurality of registers for the shader program, assessing the impact of available post-register allocation optimizations, computing, via the PU, the scoring data based on number of waves of the plurality of registers, and computing, via the PU, the number of waves for execution for the plurality of registers.

公开(公告)号：US10740074B2

公开(公告)日：2020-08-11

申请号：US16227741

申请日：2018-12-20

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Brian J. Favela ,  Todd Martin ,  Robert A. Gottlieb

IPC: G06F8/41 ,  G06T1/20

Abstract: A method and system for compiler optimization includes analyzing a representation of source code to identify an original conditional construct having both a high-latency instruction and one or more instructions dependent on the high-latency instruction in a branch of the conditional construct. A set of one or more instructions following the conditional construct in the representation of source code and independent of the high-latency instruction is selected. An optimized representation of the source code is generated, whereby the optimized representation replaces the original conditional construct with a first split conditional construct positioned prior to the selected set of one or more instructions and a second split conditional construct positioned following the selected set of one or more instructions, The method further includes generating an executable representation of the source code based on the optimized representation of the source code.

公开(公告)号：US20190179798A1

公开(公告)日：2019-06-13

申请号：US16266863

申请日：2019-02-04

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Robert A. Gottlieb ,  Christopher L. Reeve ,  Michael John Bedy

IPC: G06F15/80

CPC classification number: G06F15/8007

Abstract: A method and apparatus for scheduling instructions of a shader program for a graphics processing unit (GPU) with a fixed number of registers. The method and apparatus include computing, via a processing unit (PU), a liveness-based register usage across all basic blocks in the shader program, computing, via the PU, the range of numbers of waves of a plurality of registers for the shader program, assessing the impact of available post-register allocation optimizations, computing, via the PU, the scoring data based on number of waves of the plurality of registers, and computing, via the PU, the number of waves for execution for the plurality of registers.

公开(公告)号：US10585847B2

公开(公告)日：2020-03-10

申请号：US16266863

申请日：2019-02-04

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Robert A. Gottlieb ,  Christopher L. Reeve ,  Michael John Bedy

IPC: G06F15/80

Abstract: A method and apparatus for scheduling instructions of a shader program for a graphics processing unit (GPU) with a fixed number of registers. The method and apparatus include computing, via a processing unit (PU), a liveness-based register usage across all basic blocks in the shader program, computing, via the PU, the range of numbers of waves of a plurality of registers for the shader program, assessing the impact of available post-register allocation optimizations, computing, via the PU, the scoring data based on number of waves of the plurality of registers, and computing, via the PU, the number of waves for execution for the plurality of registers.

公开(公告)号：US11243904B2

公开(公告)日：2022-02-08

申请号：US16813336

申请日：2020-03-09

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Robert A. Gottlieb ,  Christopher L. Reeve ,  Michael John Bedy

IPC: G06F15/80

Abstract: A method and apparatus for scheduling instructions of a shader program for a graphics processing unit (GPU) with a fixed number of registers. The method and apparatus include computing, via a processing unit (PU), a liveness-based register usage across all basic blocks in the shader program, computing, via the PU, the range of numbers of waves of a plurality of registers for the shader program, assessing the impact of available post-register allocation optimizations, computing, via the PU, the scoring data based on number of waves of the plurality of registers, and computing, via the PU, the number of waves for execution for the plurality of registers.

公开(公告)号：US20200278947A1

公开(公告)日：2020-09-03

申请号：US16813336

申请日：2020-03-09

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Robert A. Gottlieb ,  Christopher L. Reeve ,  Michael John Bedy

IPC: G06F15/80

Abstract: A method and apparatus for scheduling instructions of a shader program for a graphics processing unit (GPU) with a fixed number of registers. The method and apparatus include computing, via a processing unit (PU), a liveness-based register usage across all basic blocks in the shader program, computing, via the PU, the range of numbers of waves of a plurality of registers for the shader program, assessing the impact of available post-register allocation optimizations, computing, via the PU, the scoring data based on number of waves of the plurality of registers, and computing, via the PU, the number of waves for execution for the plurality of registers.

公开(公告)号：US10198259B2

公开(公告)日：2019-02-05

申请号：US15191374

申请日：2016-06-23

Applicant: Advanced Micro Devices, Inc.

Inventor： Robert A. Gottlieb ,  Christopher L. Reeve ,  Michael John Bedy

IPC: G06F9/30 ,  G06F15/80

Abstract: A method and apparatus for scheduling instructions of a shader program for a graphics processing unit (GPU) with a fixed number of registers. The method and apparatus include computing, via a processing unit (PU), a liveness-based register usage across all basic blocks in the shader program, computing, via the PU, the range of numbers of waves of a plurality of registers for the shader program, assessing the impact of available post-register allocation optimizations, computing, via the PU, the scoring data based on number of waves of the plurality of registers, and computing, via the PU, the number of waves for execution for the plurality of registers.