公开(公告)号：US20230195644A1

公开(公告)日：2023-06-22

申请号：US17556617

申请日：2021-12-20

Applicant: Advanced Micro Devices, Inc.

Inventor： Benjamin Tsien ,  Chintan S. Patel ,  Guhan Krishnan ,  Andrew William Lueck ,  Sreenath Thangarajan

IPC: G06F12/0897

CPC classification number: G06F12/0897 ,  G06F2212/60

Abstract: A data processor includes a data fabric, a memory controller, a last level cache, and a traffic monitor. The data fabric is for routing requests between a plurality of requestors and a plurality of responders. The memory controller is for accessing a volatile memory. The last level cache is coupled between the memory controller and the data fabric. The traffic monitor is coupled to the last level cache and operable to monitor traffic between the last level cache and the memory controller, and based on detecting an idle condition in the monitored traffic, to cause the memory controller to command the volatile memory to enter self-refresh mode while the last level cache maintains an operational power state and responds to cache hits over the data fabric.

公开(公告)号：US12174747B2

公开(公告)日：2024-12-24

申请号：US17556617

申请日：2021-12-20

Applicant: Advanced Micro Devices, Inc.

Inventor： Benjamin Tsien ,  Chintan S. Patel ,  Guhan Krishnan ,  Andrew William Lueck ,  Sreenath Thangarajan

IPC: G06F12/0897

Abstract: A data processor includes a data fabric, a memory controller, a last level cache, and a traffic monitor. The data fabric is for routing requests between a plurality of requestors and a plurality of responders. The memory controller is for accessing a volatile memory. The last level cache is coupled between the memory controller and the data fabric. The traffic monitor is coupled to the last level cache and operable to monitor traffic between the last level cache and the memory controller, and based on detecting an idle condition in the monitored traffic, to cause the memory controller to command the volatile memory to enter self-refresh mode while the last level cache maintains an operational power state and responds to cache hits over the data fabric.