公开(公告)号：US20250165284A1

公开(公告)日：2025-05-22

申请号：US18518204

申请日：2023-11-22

Applicant: Advanced Micro Devices, Inc.

Inventor： Travis Boraten ,  Heather Lynn Hanson ,  Yasuko Eckert ,  Onur Kayiran

IPC: G06F9/48

Abstract: A method for collapsing operations into super operations in a computing system includes dispatching a super operation corresponding to a collapsible sequence of operations to a scheduler, performing a lookup in a super operation table for the collapsible sequence of operations in response to the super operation being picked from the scheduler, and multi-pumping the collapsible sequence of operations to a pipe operationally coupled to the scheduler. For example, the multi-pumped collapsible sequence of operations may then be sequentially executed by an execution unit. The collapsible sequence of operations may be identified as collapsible according to a set of rules.

公开(公告)号：US11837527B2

公开(公告)日：2023-12-05

申请号：US16936629

申请日：2020-07-23

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Travis Boraten

IPC: H01L23/48 ,  H01L23/525 ,  H01L25/18 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L23/481 ,  H01L23/5252 ,  H01L23/5256 ,  H01L25/18 ,  H01L25/50

Abstract: Various semiconductor chips and chip stack arrangements are disclosed. In one aspect, a semiconductor chip stack is provided that includes a first semiconductor chip and a second semiconductor chip stacked on the first semiconductor chip. The first semiconductor chip includes a first logic layer and a first semiconductor layer on the first logic layer. The first semiconductor layer has plural first through-silicon transistors operable to selectively control the transmission of data from the first semiconductor chip to the second semiconductor chip and has plural first through-silicon vias to convey control signals to the second semiconductor chip.

公开(公告)号：US20220028757A1

公开(公告)日：2022-01-27

申请号：US16936629

申请日：2020-07-23

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Travis Boraten

IPC: H01L23/48 ,  H01L25/18 ,  H01L23/525 ,  H01L25/00

Abstract: Various semiconductor chips and chip stack arrangements are disclosed. In one aspect, a semiconductor chip stack is provided that includes a first semiconductor chip and a second semiconductor chip stacked on the first semiconductor chip. The first semiconductor chip includes a first logic layer and a first semiconductor layer on the first logic layer. The first semiconductor layer has plural first through-silicon transistors operable to selectively control the transmission of data from the first semiconductor chip to the second semiconductor chip and has plural first through-silicon vias to convey control signals to the second semiconductor chip.