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公开(公告)号:US20220020680A1
公开(公告)日:2022-01-20
申请号:US16929018
申请日:2020-07-14
Applicant: Advanced Semiconductor Engineering, Inc.
Inventor: Chia Hsiu HUANG , Chun Chen CHEN , Wei Chih CHO , Shao-Lun YANG , Yu-Shun HSIEH
IPC: H01L23/498 , H01L23/00 , H01L23/31 , H01L21/48
Abstract: A lead frame includes a die paddle and a plurality of leads. The leads surround the die paddle. Each of the leads includes an inner lead portion and an outer lead portion connecting to the inner lead portion. The inner lead portion is adjacent to and spaced apart from the die paddle. A bottom surface of the inner lead portion is higher than a bottom surface of the outer lead portion. The bottom surface of the inner lead portion includes one or more supporting members disposed thereon. The one or more supporting members have a convex surface facing away from the inner lead portion.
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公开(公告)号:US20190279941A1
公开(公告)日:2019-09-12
申请号:US16421238
申请日:2019-05-23
Applicant: Advanced Semiconductor Engineering, Inc.
Inventor: Shao-Lun YANG , Yu-Shun HSIEH , Chia Yi CHENG , Hong Jie CHEN , Shih Yu HUANG
IPC: H01L23/552 , H01L23/495
Abstract: A semiconductor device package includes: (1) a lead frame including a connection element and multiple leads; (2) a package body encapsulating the lead frame, wherein the package body includes a lower surface and an upper surface opposite to the lower surface, the package body includes a cavity exposing at least one of the leads; (3) at least one conductive via disposed in the cavity of the package body, electrically connected to the connection element, and exposed from the upper surface of the package body; and (4) a conductive layer disposed on the upper surface of the package body and the conductive via.
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公开(公告)号:US20210159155A1
公开(公告)日:2021-05-27
申请号:US16693193
申请日:2019-11-22
Applicant: Advanced Semiconductor Engineering, Inc.
Inventor: Yi-Cheng HSU , Chih-Hung HSU , Mei-Lin HSIEH , Yuan-Chun CHEN , Yu-Shun HSIEH , Ko-Pu WU , Chin LI HUANG
IPC: H01L23/498 , H01L21/56 , H01L21/48 , H01L23/00
Abstract: A lead frame includes a die paddle, a plurality of leads, at least one connector and a bonding layer. The leads surround the die paddle. Each of the leads includes an inner lead portion adjacent to and spaced apart from the die paddle and an outer lead portion opposite to the inner lead portion. The connector is connected to the die paddle and the inner lead portions of the leads. The bonding layer is disposed on a lower surface of the die paddle and a lower surface of each of the outer lead portions.
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公开(公告)号:US20190122992A1
公开(公告)日:2019-04-25
申请号:US15789858
申请日:2017-10-20
Applicant: Advanced Semiconductor Engineering, Inc.
Inventor: Shao-Lun YANG , Yu-Shun HSIEH , Chia Yi CHENG , Hong Jie CHEN , Shih Yu HUANG
IPC: H01L23/552 , H01L23/495
Abstract: A semiconductor device package includes a lead frame, an electronic component, a package body, at least one conductive via and a conductive layer. The lead frame includes a paddle, a connection element and a plurality of leads. The electronic component is disposed on the paddle. The package body encapsulates the electronic component and the lead frame. The at least one conductive via is disposed in the package body, electrically connected to the connection element, and exposed from the package body. The conductive layer is disposed on the package body and the conductive via.
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