公开(公告)号：US20070018323A1

公开(公告)日：2007-01-25

申请号：US11187565

申请日：2005-07-22

Applicant: Allen Kramer

Inventor： Allen Kramer

IPC: H01L23/02

CPC classification number: H01L23/645 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/50 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05553 ,  H01L2224/48091 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10162 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/00012

Abstract: Techniques are described for reducing inductance in ball grid array (BGA) packages for integrated circuits (ICs). The BGA package comprises a set of contacts disposed near an outer edge of the BGA package that receives signal lines and isolated power and ground lines. One area of excess parasitic inductance within the BGA package is in the wire bonds that couple the set of contacts to the IC. The techniques described herein shorten the wire bonds in order to reduce the amount of parasitic inductance. The techniques include extending traces from a subset of the contacts inward into the BGA package toward the IC mounted. The wire bonds then couple the traces to the IC, thereby electrically coupling the subset of contacts to the IC. The presence of the traces substantially reduces lengths of the wire bonds relative to wire bonds that directly couple the set of contacts to the IC.

Abstract translation: 描述了用于减小用于集成电路（IC）的球栅阵列（BGA）封装中的电感的技术。 BGA封装包括设置在BGA封装的外边缘附近的一组触点，其接收信号线和隔离的电源线和接地线。 BGA封装内的过多寄生电感的一个区域是将该组触点耦合到IC的引线键。 这里描述的技术缩短了引线键合，以减少寄生电感的数量。 这些技术包括将触点的子集向内延伸到BGA封装中的迹线朝着安装的IC延伸。 接线然后将迹线耦合到IC，从而将触点的子集电耦合到IC。 迹线的存在基本上减少了将引线接合的长度相对于直接将该组触点耦合到IC的引线键合。

公开(公告)号：US6092226A

公开(公告)日：2000-07-18

申请号：US21651

申请日：1998-02-10

Applicant: Allen Kramer ,  Roger Brown ,  Eric Fischer

Inventor： Allen Kramer ,  Roger Brown ,  Eric Fischer

IPC: G01R31/3185 ,  G01R31/28

CPC classification number: G01R31/318541

Abstract: An input cell to the core logic on an electrical component and an output cell from the core logic on an electrical component are provided with a first signal path for data, a second signal path for scan data, a flip flop positioned near the pad of the core logic for selecting between said first signal path for data and second signal path for scan data. The scan data is used to input special signals or vectors to the core logic and to read the results of the scan data after it has passed through the core data and has been manipulated thereby. Several of the electrical components can be electrically connected to one another. The output cell of a first chip is electrically attached to the input cell of a second electrical component. The individual electrical components are connected on a printed circuit board and typically there are electrical conductors associated with the printed circuit board that are used to electrically connect the first chip or electrical component and the second chip or electrical component.

Abstract translation: 电气元件上的核心逻辑的输入单元和来自电气元件上的核心逻辑的输出单元被提供有用于数据的第一信号路径，用于扫描数据的第二信号路径，位于 用于在用于数据的所述第一信号路径和用于扫描数据的第二信号路径之间进行选择的核心逻辑。 扫描数据用于向核心逻辑输入特殊信号或向量，并在扫描数据通过核心数据后读取扫描数据的结果，并由此进行操作。 几个电气部件可以彼此电连接。 第一芯片的输出单元电连接到第二电气部件的输入单元。 各个电气部件连接在印刷电路板上，并且通常存在与印刷电路板相关联的用于电连接第一芯片或电气部件以及第二芯片或电气部件的电导体。