公开(公告)号：US09583218B1

公开(公告)日：2017-02-28

申请号：US14252752

申请日：2014-04-14

Applicant: Altera Corporation

Inventor： Michael D. Hutton ,  Martin Langhammer

IPC: G11C29/56 ,  G06F11/07 ,  G06F11/14 ,  G06F11/10 ,  G06F11/27 ,  G06F9/30 ,  G06F17/50 ,  H04L7/04 ,  H04L1/00 ,  G11C11/412 ,  G11C29/04

CPC classification number: G11C29/56008 ,  G06F1/10 ,  G06F9/30141 ,  G06F11/0751 ,  G06F11/10 ,  G06F11/1451 ,  G06F11/27 ,  G06F17/5054 ,  G06F2217/70 ,  G11C11/4125 ,  G11C2029/0409 ,  G11C2029/0411 ,  G11C2207/104 ,  H01L2924/00 ,  H03K19/177 ,  H03K19/17704 ,  H04L1/004 ,  H04L7/042

Abstract: Integrated circuits such as application specific integrated circuits or programmable logic devices may include sequential elements such as configurable register circuitry. Such configurable register circuitry may operate as independent registers controlled by selectable clock signals or as a single register with error detection and error correction capabilities. For example, the configurable register circuitry when operated as single register with error detection and error correction circuitry may detect and correct runtime errors caused by manufacturing and environmental variations, thereby allowing an increase in the clock rate that controls the register. If desired, the configurable register circuitry may be configured to detect single event upsets, which may enable the implementation of safe finite state machines.

Abstract translation: 诸如专用集成电路或可编程逻辑器件的集成电路可以包括诸如可配置寄存器电路的顺序元件。 这种可配置寄存器电路可以作为由可选择的时钟信号控制的独立寄存器或作为具有错误检测和纠错能力的单个寄存器来操作。 例如，当作为具有错误检测和错误校正电路的单个寄存器操作时，可配置寄存器电路可以检测和纠正由制造和环境变化引起的运行时错误，从而允许增加控制寄存器的时钟速率。 如果需要，可配置的寄存器电路可以被配置为检测单个事件的不匹配，这可以实现安全的有限状态机。

公开(公告)号：US09257982B2

公开(公告)日：2016-02-09

申请号：US13952398

申请日：2013-07-26

Applicant: Altera Corporation

Inventor： Michael D. Hutton

IPC: H03K19/003 ,  H03K19/007

Abstract: A packaged component may include an interposer and integrated circuit dies mounted on the interposer. At least one of the dies may be a radiation-hardened integrated circuit die, whereas the remaining dies may be non-radiation-hardened dies. If desired, the interposer may be a radiation-hardened interposer whereas the integrated circuit dies may be non-radiation-hardened dies. The radiation-hardened die or the radiation-hardened interposer may include monitor circuitry that is used to test non-radiation-hardened circuitry of the packaged component. Test results may be stored in a database at the monitor circuitry or transmitted to external devices such as a server. The monitor circuitry may be used to reconfigure failed circuitry or may control multiplexing circuitry in the interposer to functionally replace the failed circuitry. If desired, the monitor circuitry may adjust power consumption of non-radiation-hardened circuitry based on the test results.

公开(公告)号：US09166599B1

公开(公告)日：2015-10-20

申请号：US14212667

申请日：2014-03-14

Applicant: Altera Corporation

Inventor： Michael D. Hutton

IPC: H03K19/177

CPC classification number: H03K19/17744 ,  H03K19/17728 ,  H03K19/17736

Abstract: Integrated circuits may include logic regions configurable to perform custom functions. Interconnects may be used to rout signals throughout the integrated circuit. The logic region may be coupled to input selection circuitry for selecting and providing input signals from the interconnects to the logic regions and to output selection and routing circuitry for selecting and transmitting output signals over interconnects to other logic regions. Bypass circuitry may provide direct access to registers inside the logic regions and to the output selection and routing circuitry by bypassing the input selection circuitry and other processing circuitry inside the logic regions. Bus interconnections having logic regions performing register pipelining, wire stitching, and acting as data source/sink stations to get on and off the bus interconnections may be generated by configuring the bypass circuitry and the output selection and routing circuitry appropriately.

Abstract translation: 集成电路可以包括可配置为执行定制功能的逻辑区域。 互连可用于整个集成电路中的信号。 逻辑区域可以耦合到输入选择电路，用于选择并提供从互连到逻辑区域的输入信号，并输出选择和路由电路，用于通过互连将输出信号选择和发送到其他逻辑区域。 旁路电路可以通过绕过逻辑区域内的输入选择电路和其它处理电路来提供对逻辑区域内的寄存器和输出选择和路由电路的直接访问。 可以通过适当地配置旁路电路和输出选择和布线电路来产生具有执行寄存器流水线，线缝合并且充当数据源/汇点以接通和断开总线互连的逻辑区的总线互连。

公开(公告)号：US20150028918A1

公开(公告)日：2015-01-29

申请号：US13952398

申请日：2013-07-26

Applicant: Altera Corporation

Inventor： Michael D. Hutton

IPC: H03K19/003

CPC classification number: H03K19/0033

Abstract: A packaged component may include an interposer and integrated circuit dies mounted on the interposer. At least one of the dies may be a radiation-hardened integrated circuit die, whereas the remaining dies may be non-radiation-hardened dies. If desired, the interposer may be a radiation-hardened interposer whereas the integrated circuit dies may be non-radiation-hardened dies. The radiation-hardened die or the radiation-hardened interposer may include monitor circuitry that is used to test non-radiation-hardened circuitry of the packaged component. Test results may be stored in a database at the monitor circuitry or transmitted to external devices such as a server. The monitor circuitry may be used to reconfigure failed circuitry or may control multiplexing circuitry in the interposer to functionally replace the failed circuitry. If desired, the monitor circuitry may adjust power consumption of non-radiation-hardened circuitry based on the test results.

Abstract translation: 封装的部件可以包括插入器和安装在插入器上的集成电路管芯。 至少一个模具可以是辐射硬化的集成电路模具，而剩余的模具可以是非辐射硬化的模具。 如果需要，插入器可以是辐射硬化的插入器，而集成电路管芯可以是非辐射硬化的管芯。 辐射硬化的芯片或辐射硬化的插入器可以包括用于测试封装部件的非辐射硬化电路的监视器电路。 测试结果可以存储在监视器电路的数据库中或传输到诸如服务器的外部设备。 监视器电路可用于重新配置故障电路，或者可以控制插入器中的多路复用电路以功能地替换故障电路。 如果需要，监控电路可以基于测试结果调整非辐射硬化电路的功耗。

公开(公告)号：US20200257651A1

公开(公告)日：2020-08-13

申请号：US16859728

申请日：2020-04-27

Applicant: Altera Corporation

Inventor： Michael D. Hutton ,  Anargyros Krikelis

IPC: G06F15/76 ,  G06F15/78

Abstract: The present invention provides a hybrid programmable logic device which includes a programmable field programmable gate array logic fabric and a many-core distributed processing subsystem. The device integrates both a fabric of programmable logic elements and processors in the same device, i.e., the same chip. The programmable logic elements may be sized and arranged such that place and route tools can address the processors and logic elements as a homogenous routing fabric. The programmable logic elements may provide hardware acceleration functions to the processors that can be defined after the device is fabricated. The device may include scheduling circuitry that can schedule the transmission of data on horizontal and vertical connectors in the logic fabric to transmit data between the programmable logic elements and processor in an asynchronous manner.

公开(公告)号：US09294092B2

公开(公告)日：2016-03-22

申请号：US13952398

申请日：2013-07-26

Applicant: Altera Corporation

Inventor： Michael D. Hutton

IPC: H03K19/003 ,  H03K19/007

CPC classification number: H03K19/0033

Abstract: A packaged component may include an interposer and integrated circuit dies mounted on the interposer. At least one of the dies may be a radiation-hardened integrated circuit die, whereas the remaining dies may be non-radiation-hardened dies. If desired, the interposer may be a radiation-hardened interposer whereas the integrated circuit dies may be non-radiation-hardened dies. The radiation-hardened die or the radiation-hardened interposer may include monitor circuitry that is used to test non-radiation-hardened circuitry of the packaged component. Test results may be stored in a database at the monitor circuitry or transmitted to external devices such as a server. The monitor circuitry may be used to reconfigure failed circuitry or may control multiplexing circuitry in the interposer to functionally replace the failed circuitry. If desired, the monitor circuitry may adjust power consumption of non-radiation-hardened circuitry based on the test results.

Abstract translation: 封装的部件可以包括插入器和安装在插入器上的集成电路管芯。 至少一个模具可以是辐射硬化的集成电路模具，而剩余的模具可以是非辐射硬化的模具。 如果需要，插入器可以是辐射硬化的插入器，而集成电路管芯可以是非辐射硬化的管芯。 辐射硬化的芯片或辐射硬化的插入器可以包括用于测试封装部件的非辐射硬化电路的监视器电路。 测试结果可以存储在监视器电路的数据库中或传输到诸如服务器的外部设备。 监视器电路可用于重新配置故障电路，或者可以控制插入器中的多路复用电路以功能地替换故障电路。 如果需要，监控电路可以基于测试结果调整非辐射硬化电路的功耗。

公开(公告)号：US09292474B1

公开(公告)日：2016-03-22

申请号：US13957113

申请日：2013-08-01

Applicant: Altera Corporation

Inventor： Erhard Joachim Pistorius ,  Michael D. Hutton

IPC: G06F7/50 ,  G06F17/10

CPC classification number: G06F17/10 ,  G06F7/507 ,  G06F7/508

Abstract: Hybrid adder circuitry is provided for integrated circuits such as programmable integrated circuits. The hybrid adder may combine the capabilities of multiple adder architectures. Hybrid adders may include carry select and carry ripple adder circuits. The adder circuits may be combined using a carry look-ahead architecture. Adder functionality may be implemented using the resources of logic regions on the programmable integrated circuits. Each logic region may include combinatorial logic such as look-up table logic and register circuitry. The hybrid adder circuitry may receive input words to be added from the combinatorial circuitry and may produce corresponding arithmetic sum output signals to the register circuitry.

公开(公告)号：US09178513B1

公开(公告)日：2015-11-03

申请号：US14135466

申请日：2013-12-19

Applicant: Altera Corporation

Inventor： Michael D. Hutton ,  David Lewis

IPC: H03K19/177 ,  H03K19/00

CPC classification number: H03K19/17776 ,  H03K19/17748 ,  H03K19/1776

Abstract: An integrated circuit may have configurable storage blocks. Multiple configurable storage blocks may share one or more internal address busses with selected configurable storage blocks having access a given address bus. An address bus may be unidirectional or bidirectional and may convey the same address signal from one configurable address block to another or to several other configurable storage blocks. Tri-state buffers or multiplexers may selectively couple or decouple the address bus between configurable storage blocks. Redundant address bus paths may bypass configurable address blocks in neighboring rows or columns allowing for disabling the respective row or column. The address bus may further have pipeline registers to allow for pipelined access to configurable storage blocks.

Abstract translation: 集成电路可以具有可配置的存储块。 多个可配置存储块可以与具有访问给定地址总线的选定的可配置存储块共享一个或多个内部地址总线。 地址总线可以是单向的或双向的，并且可以将相同的地址信号从一个可配置地址块传送到另一个或另一个可配置的存储块。 三态缓冲器或多路复用器可以在可配置存储块之间选择性地耦合或去耦地址总线。 冗余地址总线路径可以绕过相邻行或列中的可配置地址块，允许禁用相应的行或列。 地址总线可以进一步具有流水线寄存器以允许对可配置存储块的流水线访问。

公开(公告)号：US09172378B1

公开(公告)日：2015-10-27

申请号：US14068386

申请日：2013-10-31

Applicant: ALTERA CORPORATION

Inventor： Michael D. Hutton ,  Gregg William Baeckler ,  Jinyong Yuan ,  Chris Wysocki ,  Pouyan Djahani

IPC: G06F17/50 ,  H03K19/173

CPC classification number: H03K19/173 ,  H03K19/1736 ,  H03K19/17728

Abstract: A programmable logic device architecture having logic elements with dedicated hardware to configure the look up tables of the logic element to either perform logic functions or to operate as a register for pipelining. The programmable logic device includes a general interconnect and a plurality of logic array blocks interconnected by the general interconnect. Each of the plurality of logic blocks further includes one or more logic elements. The logic elements each include a first look up table, a second look up table, and dedicated hardware within the logic element to configure the first look table and the second look up table as a register without having to use the general interconnect. In one embodiment, the dedicated hardware includes a plurality of dedicated interconnects within the logic element to configure the two look up tables as a pair of cross coupled muxes or latches when configured as a register.

Abstract translation: 具有逻辑元件的可编程逻辑器件架构具有专用硬件以配置逻辑元件的查找表以执行逻辑功能或作为用于流水线化的寄存器来操作。 可编程逻辑器件包括通用互连和通过一般互连互连的多个逻辑阵列块。 多个逻辑块中的每一个还包括一个或多个逻辑元件。 逻辑元件各自包括第一查询表，第二查询表和逻辑元件内的专用硬件，以将第一查询表和第二查询表配置为寄存器而不必使用通用互连。 在一个实施例中，专用硬件包括逻辑元件内的多个专用互连，以在配置为寄存器时将两个查找表配置为一对交叉耦合的多路复用器或锁存器。

公开(公告)号：US20140111247A1

公开(公告)日：2014-04-24

申请号：US13656262

申请日：2012-10-19

Applicant: Altera Corporation

Inventor： Michael D. Hutton

IPC: H03K19/173

CPC classification number: H03K19/17744 ,  H03K19/17728 ,  H03K19/17736

Abstract: Integrated circuits may include logic regions configurable to perform custom functions. Interconnects may be used to route signals throughout the integrated circuit. The logic region may be coupled to input selection circuitry for selecting and providing input signals from the interconnects to the logic regions and to output selection and routing circuitry for selecting and transmitting output signals over interconnects to other logic regions. Bypass circuitry may provide direct access to registers inside the logic regions and to the output selection and routing circuitry by bypassing the input selection circuitry and other processing circuitry inside the logic regions. Bus interconnections having logic regions performing register pipelining, wire stitching, and acting as data source/sink stations to get on and off the bus interconnections may be generated by configuring the bypass circuitry and the output selection and routing circuitry appropriately.

Abstract translation: 集成电路可以包括可配置为执行定制功能的逻辑区域。 互连可用于在整个集成电路中路由信号。 逻辑区域可以耦合到输入选择电路，用于选择并提供从互连到逻辑区域的输入信号，并输出选择和路由电路，用于通过互连将输出信号选择和发送到其他逻辑区域。 旁路电路可以通过绕过逻辑区域内的输入选择电路和其它处理电路来提供对逻辑区域内的寄存器和输出选择和路由电路的直接访问。 可以通过适当地配置旁路电路和输出选择和布线电路来产生具有执行寄存器流水线，线缝合并且充当数据源/汇点以接通和断开总线互连的逻辑区的总线互连。