公开(公告)号：US10146249B2

公开(公告)日：2018-12-04

申请号：US15274597

申请日：2016-09-23

Applicant: Altera Corporation

Inventor： Han Hua Leong ,  Ru Yin Ng ,  Geok Sun Chong ,  David W. Mendel

IPC: H04L7/00 ,  G06F1/08 ,  G06F13/40

Abstract: A control system controls First-In First-Out (FIFO) settings of a receiving system. The control system includes a FIFO settings controller that receives a first signal indicative of a first frequency of data received by the receiving system. The FIFO settings controller receives a second signal indicative of a second frequency of a clock that reads the data received by the receiving system. The FIFO settings controller determines a difference (e.g., a parts-per-million (PPM) difference) between the first frequency and the second frequency. The FIFO settings controller sends a third signal indicative of instructions to adjust FIFO configuration settings based on the PPM difference.

公开(公告)号：US20180088622A1

公开(公告)日：2018-03-29

申请号：US15274597

申请日：2016-09-23

Applicant: Altera Corporation

Inventor： Han Hua Leong ,  Ru Yin Ng ,  Geok Sun Chong ,  David W. Mendel

IPC: G06F1/08 ,  G06F13/40

CPC classification number: G06F1/08 ,  G06F13/4068

Abstract: A control system controls First-In First-Out (FIFO) settings of a receiving system. The control system includes a FIFO settings controller that receives a first signal indicative of a first frequency of data received by the receiving system. The FIFO settings controller receives a second signal indicative of a second frequency of a clock that reads the data received by the receiving system. The FIFO settings controller determines a difference (e.g., a parts-per-million (PPM) difference) between the first frequency and the second frequency. The FIFO settings controller sends a third signal indicative of instructions to adjust FIFO configuration settings based on the PPM difference.

公开(公告)号：US09891653B2

公开(公告)日：2018-02-13

申请号：US14739441

申请日：2015-06-15

Applicant: Altera Corporation

Inventor： Ru Yin Ng ,  Gary Wallichs ,  Keith Duwel

IPC: G06F1/10 ,  G06F1/12 ,  G06F13/42

CPC classification number: G06F1/10 ,  G06F1/12 ,  G06F13/4278

Abstract: An integrated circuit die includes interface and adapter circuits. The interface circuit exchanges data with an external device outside the integrated circuit die using a first clock signal. The interface circuit has a clock signal generation circuit to generate the first clock signal based on a second clock signal. The adapter circuit exchanges the data with the interface circuit. A frequency of the second clock signal is changed in response to an indication of a change in a data rate of the data. The adapter circuit causes the interface circuit to provide an adjustment to the first clock signal after the frequency of the second clock signal changes. The adapter circuit prevents the exchange of the data between the interface circuit and the external device until the adapter circuit receives an indication of completion of the adjustment to the first clock signal.

公开(公告)号：US20160363954A1

公开(公告)日：2016-12-15

申请号：US14739441

申请日：2015-06-15

Applicant: Altera Corporation

Inventor： Ru Yin Ng ,  Gary Wallichs ,  Keith Duwel

IPC: G06F1/10 ,  G06F1/12

CPC classification number: G06F1/10 ,  G06F1/12 ,  G06F13/4278

Abstract: An integrated circuit die includes interface and adapter circuits. The interface circuit exchanges data with an external device outside the integrated circuit die using a first clock signal. The interface circuit has a clock signal generation circuit to generate the first clock signal based on a second clock signal. The adapter circuit exchanges the data with the interface circuit. A frequency of the second clock signal is changed in response to an indication of a change in a data rate of the data. The adapter circuit causes the interface circuit to provide an adjustment to the first clock signal after the frequency of the second clock signal changes. The adapter circuit prevents the exchange of the data between the interface circuit and the external device until the adapter circuit receives an indication of completion of the adjustment to the first clock signal.

Abstract translation: 集成电路管芯包括接口和适配器电路。 接口电路使用第一时钟信号与集成电路管芯外部的外部设备交换数据。 接口电路具有时钟信号发生电路，用于基于第二时钟信号产生第一时钟信号。 适配器电路与接口电路交换数据。 响应于数据的数据速率的变化的指示，第二时钟信号的频率被改变。 适配器电路使得接口电路在第二时钟信号的频率变化之后提供对第一时钟信号的调整。 适配器电路防止接口电路和外部设备之间的数据交换，直到适配器电路接收到对第一时钟信号的调整完成的指示。