公开(公告)号：US20180025100A1

公开(公告)日：2018-01-25

申请号：US15214354

申请日：2016-07-19

Applicant: Altera Corporation

Inventor： Sergey Gribok

IPC: G06F17/50 ,  G06F7/52

CPC classification number: G06F17/505 ,  G06F7/52 ,  G06F7/535 ,  G06F8/443 ,  G06F17/5054 ,  G06F2207/5356 ,  G06F2217/84

Abstract: A method for designing a system on a target device includes identifying components in a netlist that perform a division operation. The netlist is modified during synthesis to utilize other components to compute a result of the division operation by performing a multiplication operation.

公开(公告)号：US10223488B2

公开(公告)日：2019-03-05

申请号：US15214354

申请日：2016-07-19

Applicant: Altera Corporation

Inventor： Sergey Gribok

IPC: G06F17/50 ,  G06F7/52 ,  G06F7/535 ,  G06F8/41

Abstract: A method for designing a system on a target device includes identifying components in a netlist that perform a division operation. The netlist is modified during synthesis to utilize other components to compute a result of the division operation by performing a multiplication operation.

公开(公告)号：US20250061257A1

公开(公告)日：2025-02-20

申请号：US18936210

申请日：2024-11-04

Applicant: Altera Corporation

Inventor： Bee Yee Ng ,  Gaik Ming Chan ,  Sergey Gribok ,  Scott Weber

IPC: G06F30/343

Abstract: A system includes a hard network-on-chip (NOC) and lookup table random access memory (LUTRAM) circuits usable as logic gates in a user design for an integrated circuit and reprogrammable in a user mode of the integrated circuit through the hard NOC. The LUTRAM circuits are reconfigurable during the user mode of the integrated circuit by providing a bit through the hard NOC for storage in the one of the LUTRAM circuits.