公开(公告)号：US20250061257A1

公开(公告)日：2025-02-20

申请号：US18936210

申请日：2024-11-04

Applicant: Altera Corporation

Inventor： Bee Yee Ng ,  Gaik Ming Chan ,  Sergey Gribok ,  Scott Weber

IPC: G06F30/343

Abstract: A system includes a hard network-on-chip (NOC) and lookup table random access memory (LUTRAM) circuits usable as logic gates in a user design for an integrated circuit and reprogrammable in a user mode of the integrated circuit through the hard NOC. The LUTRAM circuits are reconfigurable during the user mode of the integrated circuit by providing a bit through the hard NOC for storage in the one of the LUTRAM circuits.

公开(公告)号：US10394990B1

公开(公告)日：2019-08-27

申请号：US15277356

申请日：2016-09-27

Applicant: Altera Corporation

Inventor： Kalen Brunham ,  Kevin Nealis ,  Yi Peng ,  Scott Weber

IPC: G06F17/50

Abstract: Devices and methods for initializing one or more registers of a programmable integrated circuit (IC) to store an initial condition value are provided. A first bitstream that programs the region of the IC to supply the initial condition value to the one or more registers is first programmed on the IC. Then, once the registers are initialized with the initial condition value, a second bitstream is subsequently programmed to the region of the IC to supply values associated with a function of the design to the one or more registers.

公开(公告)号：US09941867B1

公开(公告)日：2018-04-10

申请号：US15270437

申请日：2016-09-20

Applicant: ALTERA CORPORATION

Inventor： Scott Weber

IPC: H03K3/356 ,  H03K19/177

CPC classification number: H03K3/356104 ,  H03K3/012 ,  H03K19/17716 ,  H03K19/1776

Abstract: One embodiment relates to a pulse latch that includes a latch control logic circuit and a pulse latch circuit. The latch control logic circuit generates a plurality of control signals and selects a control signal of the plurality of control signals to output to the pulse latch circuit. Each control signal of the plurality of control signals causes the pulse latch circuit to operate in a different operating mode. Another embodiment relates to a method of generating control signaling for a pulse latch. A clock signal and a shifted clock signal are received. A plurality of inputs to a multiplexor are generated using the clock signal and the shifted clock signal. An input of the plurality of inputs is selected as an output of the multiplexor. The input is selected by the multiplexor using a plurality of multiplexor configuration bits.