公开(公告)号：US20200341918A1

公开(公告)日：2020-10-29

申请号：US16896157

申请日：2020-06-08

Applicant: Altera Corporation

Inventor： Steven Perry

IPC: G06F13/16 ,  H03K19/17728 ,  H03K19/17748 ,  H03K19/17736 ,  G06F30/34 ,  G06F30/327 ,  H03K19/1776 ,  G06F13/42

Abstract: Systems and methods for configuring a SPA are disclosed. The SPA comprises a plurality of input ports, a plurality of data memory units, signal processing circuitry, and an enable block including at least two counters. Each counter determines an amount of unprocessed data that is stored in a respective one of the plurality of data memory units, and the enable block is configured to disable the signal processing circuitry until a predetermined amount of data is received over the input ports.

公开(公告)号：US09026967B1

公开(公告)日：2015-05-05

申请号：US14245228

申请日：2014-04-04

Applicant: Altera Corporation

Inventor： Steven Perry

IPC: G06F17/50

CPC classification number: G06F17/505 ,  G06F17/5054

Abstract: A method for designing a system to be implemented on a target device includes generating a register transfer language (RTL) representation of the system from a description of the system without pipelined delays. The RTL representation of the system includes pipelined delays to facilitate timing of the system as implemented on a target device identified by a designer.

Abstract translation: 用于设计要在目标设备上实现的系统的方法包括从系统的描述生成系统的寄存器传送语言（RTL）表示，而不需要流水线延迟。 该系统的RTL表示包括流水线延迟以便于在由设计者识别的目标设备上实现的系统的定时。

公开(公告)号：US10268605B1

公开(公告)日：2019-04-23

申请号：US14686326

申请日：2015-04-14

Applicant: Altera Corporation

Inventor： Steven Perry

IPC: G06F13/16 ,  G06F13/42

Abstract: Systems and methods for configuring a SPA are disclosed. The SPA comprises a plurality of input ports, a plurality of data memory units, signal processing circuitry, and an enable block including at least two counters. Each counter determines an amount of unprocessed data that is stored in a respective one of the plurality of data memory units, and the enable block is configured to disable the signal processing circuitry until a predetermined amount of data is received over the input ports.

公开(公告)号：US08739102B1

公开(公告)日：2014-05-27

申请号：US13890804

申请日：2013-05-09

Applicant: Altera Corporation

Inventor： Steven Perry

IPC: G06F17/50

CPC classification number: G06F17/505 ,  G06F17/5054

Abstract: A method for designing a system to be implemented on a target device includes generating a register transfer language (RTL) representation of the system from a description of the system without pipelined delays. The RTL representation of the system includes pipelined delays to facilitate timing of the system as implemented on a target device identified by a designer.

Abstract translation: 用于设计要在目标设备上实现的系统的方法包括从系统的描述生成系统的寄存器传送语言（RTL）表示，而不需要流水线延迟。 该系统的RTL表示包括流水线延迟以便于在由设计者识别的目标设备上实现的系统的定时。

公开(公告)号：US09985635B2

公开(公告)日：2018-05-29

申请号：US15589688

申请日：2017-05-08

Applicant: Altera Corporation

Inventor： Steven Perry

IPC: H03K19/177 ,  G06F17/50

CPC classification number: H03K19/17728 ,  G06F17/505 ,  G06F17/5054 ,  H03K19/17736 ,  H03K19/17748 ,  H03K19/1776

Abstract: Systems and methods for configuring circuitry for use with a field programmable gate array (FPGA) are disclosed. The circuitry includes an array of signal processing accelerators (SPAs) and an array of network nodes. The array of SPAs is separate from a field programmable gate array (FPGA), and the array of SPAs is configured to receive input signals from the FPGA. The array of network nodes controllably route the input signals to the array of SPAs.

公开(公告)号：US09619423B1

公开(公告)日：2017-04-11

申请号：US14066447

申请日：2013-10-29

Applicant: ALTERA CORPORATION

Inventor： Steven Perry

IPC: G06F12/00 ,  G06F13/40 ,  G06F12/06 ,  G06F12/0831

CPC classification number: G06F13/404 ,  G06F12/0833

Abstract: Systems and devices are provided for broadcasting a message to addressed logic blocks in lieu of, or in addition to, programming individual status registers of an integrated circuit. One such device may be an integrated circuit that includes a broadcast bus and addressed logic blocks. The broadcast bus may broadcast an addressed message that includes content and a target address. Each of the addressed logic blocks may receive the addressed message from the broadcast bus and use the content of the addressed message only when the target address matches an address assigned to that logic block.

公开(公告)号：US10372655B1

公开(公告)日：2019-08-06

申请号：US15463993

申请日：2017-03-20

Applicant: ALTERA CORPORATION

Inventor： Steven Perry

IPC: G06F12/00 ,  G06F13/40 ,  G06F15/78 ,  G06F12/06

Abstract: Systems and devices are provided for broadcasting a message to addressed logic blocks in lieu of, or in addition to, programming individual status registers of an integrated circuit. One such device may be an integrated circuit that includes a broadcast bus and addressed logic blocks. The broadcast bus may broadcast an addressed message that includes content and a target address. Each of the addressed logic blocks may receive the addressed message from the broadcast bus and use the content of the addressed message only when the target address matches an address assigned to that logic block.

公开(公告)号：US20190171591A1

公开(公告)日：2019-06-06

申请号：US16169995

申请日：2018-10-24

Applicant: Altera Corporation

Inventor： Steven Perry

IPC: G06F13/16 ,  G06F13/42

Abstract: Systems and methods for configuring a SPA are disclosed. The SPA comprises a plurality of input ports, a plurality of data memory units, signal processing circuitry, and an enable block including at least two counters. Each counter determines an amount of unprocessed data that is stored in a respective one of the plurality of data memory units, and the enable block is configured to disable the signal processing circuitry until a predetermined amount of data is received over the input ports.

公开(公告)号：US09553591B2

公开(公告)日：2017-01-24

申请号：US14492717

申请日：2014-09-22

Applicant: Altera Corporation

Inventor： Steven Perry ,  Martin Langhammer ,  Richard Maiden

IPC: G06F17/10 ,  H03K19/177 ,  G06F1/02 ,  G06F17/50

CPC classification number: H03K19/17748 ,  G06F1/02 ,  G06F17/505 ,  G06F17/5054 ,  H03K19/1776

Abstract: Systems and methods of configuring a programmable integrated circuit. An array of signal processing accelerators (SPAs) is included in the programmable integrated circuit. The array of SPAs is separate from a field programmable gate array (FPGA), and the array of SPAs is configured to receive input data from the FPGA and is programmable to perform at least a filtering function on the input data to obtain output data.

Abstract translation: 配置可编程集成电路的系统和方法。 信号处理加速器（SPAs）阵列包含在可编程集成电路中。 SPA阵列与现场可编程门阵列（FPGA）分离，并且SPA阵列被配置为从FPGA接收输入数据，并且可编程为至少对输入数据执行滤波功能以获得输出数据。

公开(公告)号：US09229909B1

公开(公告)日：2016-01-05

申请号：US13667345

申请日：2012-11-02

Applicant: Altera Corporation

Inventor： Steven Perry

IPC: G06F17/14

CPC classification number: G06F17/142

Abstract: A method for designing a discrete Fourier transform (DFT) unit in a system on a target device includes identifying a number of DFT engines to implement in the DFT unit in response to a data throughput rate, a clock rate of the system, a size of a DFT, and radix of each of the DFT engines.

Abstract translation: 用于在目标设备上的系统中设计离散傅里叶变换（DFT）单元的方法包括：响应于数据吞吐率，系统的时钟速率，系统的时钟速率，识别在DFT单元中实现的DFT引擎的数量 每个DFT引擎的DFT和基数。