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公开(公告)号：US20190026497A1
公开(公告)日：2019-01-24
申请号：US16140528
申请日：2018-09-24
Applicant: Altera Corporation
Inventor： Bruce Pedersen , Ting Lu , Brian Wong , Alok Doshi , Yun Sum Wong
Abstract: An integrated circuit includes a control circuit and a one-time programmable circuit. The control circuit determines if the one-time programmable circuit is programmed in response to an attempt to access a mode of the integrated circuit after the integrated circuit powers up. The control circuit generates a signal to indicate to a user of the integrated circuit that the mode of the integrated circuit has been previously accessed if the control circuit determines that the one-time programmable circuit has been programmed to indicate a previous access to the mode of the integrated circuit.
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Patent Agency Ranking
公开(公告)号：US20170257222A1
公开(公告)日：2017-09-07
申请号：US15061622
申请日：2016-03-04
Applicant: Altera Corporation
Inventor： Bruce Pedersen , Ting Lu , Brian Wong , Alok Doshi , Yun Sum Wong
CPC classification number: G06F21/70 , G06F1/26 , G06F3/0679 , G06F2206/1014 , G09C1/00 , H04L9/0866 , H04L9/3278
Abstract: An integrated circuit includes a control circuit, a one-time programmable circuit, and a security feature. The control circuit determines if the one-time programmable circuit is programmed in response to a request by a user of the integrated circuit to access the security feature. The control circuit generates a signal to indicate to the user of the integrated circuit that the security feature has been previously accessed if the control circuit determines that the one-time programmable circuit has been programmed to indicate a previous access to the security feature. The control circuit causes the one-time programmable circuit to be programmed in response to the request if the control circuit determines that the one-time programmable circuit has not been programmed.
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公开(公告)号：US09946826B1
公开(公告)日：2018-04-17
申请号：US14843313
申请日：2015-09-02
Applicant: Altera Corporation
Inventor： Sean Atsatt , Ting Lu , Dana How , Herman Schmit
IPC: G06F17/50
CPC classification number: G06F17/505 , G06F17/5054
Abstract: In server virtualization, the resources of an integrated circuit are partitioned into smaller portions, and each of these smaller portions is then operated independently. Software is used to represent the smaller portions as virtual environments. For the purpose of server virtualization, an integrated circuit may include several different circuit designs, each implemented in a secure partition in the integrated circuit. The operation of the circuit design implementations in the integrated circuit may require that each circuit design implementation can be verified as un-altered and from the respective user or owner and as having been approved by the integrated circuit owner and/or the circuit design implementation owner. The operation of the circuit design implementations in the integrated circuit may require that each circuit design implementation can be operated securely and independently of the other circuit design implementations in the integrated circuit.
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公开(公告)号：US10657291B2
公开(公告)日：2020-05-19
申请号：US16140528
申请日：2018-09-24
Applicant: Altera Corporation
Inventor： Bruce Pedersen , Ting Lu , Brian Wong , Alok Doshi , Yun Sum Wong
Abstract: An integrated circuit includes a control circuit and a one-time programmable circuit. The control circuit determines if the one-time programmable circuit is programmed in response to an attempt to access a mode of the integrated circuit after the integrated circuit powers up. The control circuit generates a signal to indicate to a user of the integrated circuit that the mode of the integrated circuit has been previously accessed if the control circuit determines that the one-time programmable circuit has been programmed to indicate a previous access to the mode of the integrated circuit.
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公开(公告)号：US10228415B1
公开(公告)日：2019-03-12
申请号：US15277494
申请日：2016-09-27
Applicant: Altera Corporation
Inventor： Wei Yee Koay , Ting Lu , Ka Bo Wong , Rajiv Kumar
IPC: G01R31/28 , H03K17/22 , H03K19/177 , G01R19/165 , G06F21/87
Abstract: Test circuitry for providing security in an integrated circuit includes a control circuit and a test power-on-reset circuit. The control circuit determines whether the integrated circuit is configured in a non-secure condition, and that generates a control signal in response to the non-secure condition. Accordingly, the test power-on-reset circuit selectively disables a power-on-reset circuit on the integrated circuit in response the control signal during test operations. The test power-on-reset circuit receives control instructions from the control circuit, and produces a test power-on-reset output according to the control instructions. The integrated circuit includes a logic gate that receives the test power-on-reset output and a power-on-reset signal from the power-on-reset circuit and generates an output signal for bypassing operations of the power-on-reset circuit on the integrated circuit.
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公开(公告)号：US10095889B2
公开(公告)日：2018-10-09
申请号：US15061622
申请日：2016-03-04
Applicant: Altera Corporation
Inventor： Bruce Pedersen , Ting Lu , Brian Wong , Alok Doshi , Yun Sum Wong
Abstract: An integrated circuit includes a control circuit, a one-time programmable circuit, and a security feature. The control circuit determines if the one-time programmable circuit is programmed in response to a request by a user of the integrated circuit to access the security feature. The control circuit generates a signal to indicate to the user of the integrated circuit that the security feature has been previously accessed if the control circuit determines that the one-time programmable circuit has been programmed to indicate a previous access to the security feature. The control circuit causes the one-time programmable circuit to be programmed in response to the request if the control circuit determines that the one-time programmable circuit has not been programmed.
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