公开(公告)号：US09507900B2

公开(公告)日：2016-11-29

申请号：US14246970

申请日：2014-04-07

Applicant: Altera Corporation

Inventor： Andrew Caldwell ,  Herman Schmit ,  Steven Teig

IPC: G06F17/50 ,  H03K19/173 ,  H03K19/177

CPC classification number: G06F17/5054 ,  G06F17/505 ,  H03K19/1737 ,  H03K19/177

Abstract: Some embodiments of the invention provide a configurable integrated circuit (“IC”). The configurable IC includes a set of multiplexers that each has a set of input terminals, a set of output terminals, and a set of select terminals. The set of multiplexers includes a group of multiplexers, where at least one input terminal of each multiplexer in the group is a permanently inverting input terminal. During at least a set of cycles during the operation of the configurable IC, several multiplexers in the group of multiplexers are used to implement a particular function.

Abstract translation: 本发明的一些实施例提供了可配置的集成电路（“IC”）。 可配置IC包括一组多路复用器，每组具有一组输入端子，一组输出端子和一组选择端子。 该组多路复用器包括一组多路复用器，其中组中的每个多路复用器的至少一个输入端是永久反相输入端。 在可配置IC的操作期间的至少一组周期期间，使用多路复用器组中的多个多路复用器来实现特定功能。

公开(公告)号：US09369363B2

公开(公告)日：2016-06-14

申请号：US14735678

申请日：2015-06-10

Applicant: ALTERA CORPORATION

Inventor： Herman Schmit

IPC: G06F1/06 ,  H04L12/26 ,  G06F13/42 ,  H04L7/00 ,  H04L12/863 ,  H04J3/06

CPC classification number: H04L43/0864 ,  G06F13/42 ,  H04J3/0667 ,  H04J3/0697 ,  H04L7/005 ,  H04L47/6225

Abstract: One embodiment relates to a method for determining a latency of a network port. Read and write pointers for a FIFO are sampled at the same time. An average difference between a plurality of samples of the read and write pointers is determined. Another embodiment relates to an apparatus for providing timestamps to packets at a network port. Registers sample read and write pointers of a FIFO using a sampling clock. Logic circuitry determines an average difference between the read and write pointers, and timestamping circuitry receives the average difference and inserts timestamps into packets. Other embodiments and features are also disclosed.

公开(公告)号：US09118566B1

公开(公告)日：2015-08-25

申请号：US13764601

申请日：2013-02-11

Applicant: ALTERA CORPORATION

Inventor： David W. Mendel ,  Herman Schmit

IPC: H04W24/00 ,  H04L12/26

CPC classification number: H04L43/106 ,  H04L43/0858

Abstract: One embodiment relates to a method of determining an arrival time of a data packet which has data striped across a plurality of lanes of a multi-lane link. Word arrival times for the words of the data packet are determined, each word arrival time corresponding to an arrival time of a word of the data packet at an individual lane of the multi-lane link. The arrival time of the data packet is determined using a predetermined function of the word arrival times. Another embodiment relates to a receiver circuit that determines an arrival time of a data packet which has data striped across a plurality of lanes of a multi-lane link. Other embodiments and features are also disclosed.

Abstract translation: 一个实施例涉及一种确定数据分组的到达时间的方法，该数据分组具有跨多通道链路的多个通道的条带。 确定数据包的字的字到达时间，每个字的到达时间对应于多车道链路的单独车道上的数据包的字的到达时间。 使用字到达时间的预定函数来确定数据分组的到达时间。 另一个实施例涉及一种接收机电路，其确定数据分组的到达时间，该数据分组具有穿过多通道链路的多个通道的条带。 还公开了其它实施例和特征。

公开(公告)号：US09946826B1

公开(公告)日：2018-04-17

申请号：US14843313

申请日：2015-09-02

Applicant: Altera Corporation

Inventor： Sean Atsatt ,  Ting Lu ,  Dana How ,  Herman Schmit

IPC: G06F17/50

CPC classification number: G06F17/505 ,  G06F17/5054

Abstract: In server virtualization, the resources of an integrated circuit are partitioned into smaller portions, and each of these smaller portions is then operated independently. Software is used to represent the smaller portions as virtual environments. For the purpose of server virtualization, an integrated circuit may include several different circuit designs, each implemented in a secure partition in the integrated circuit. The operation of the circuit design implementations in the integrated circuit may require that each circuit design implementation can be verified as un-altered and from the respective user or owner and as having been approved by the integrated circuit owner and/or the circuit design implementation owner. The operation of the circuit design implementations in the integrated circuit may require that each circuit design implementation can be operated securely and independently of the other circuit design implementations in the integrated circuit.

公开(公告)号：US09385724B1

公开(公告)日：2016-07-05

申请号：US14045658

申请日：2013-10-03

Applicant: Altera Corporation

Inventor： Herman Schmit ,  Jiefan Zhang

IPC: G06F1/00 ,  H03K19/173 ,  H03K3/02 ,  G11C7/10

CPC classification number: H03K19/1737 ,  G11C7/10 ,  G11C7/1045 ,  G11C7/106 ,  G11C7/22 ,  H03K3/02 ,  H03K19/173 ,  H03K19/17736 ,  H03K19/1776

Abstract: Integrated circuits such as application specific circuits or programmable logic devices may include specialized blocks such as configurable storage blocks and configurable processing blocks. Such specialized blocks may be controlled by clock signals and operated at single data rate or at double data rate. For instance, configurable storage blocks may be configured to use a double data rate communications scheme or a single data rate communication scheme to communicate data with other blocks. Configurable processing blocks may be configured to process data at a double data rate or a single data rate. Furthermore, configurable processing blocks that include accumulator circuitry may be configured to perform one accumulation at a single data rate or at a double data rate. Such configurable processing blocks may also be configured to perform two accumulations at a single data rate.

Abstract translation: 诸如专用电路或可编程逻辑器件的集成电路可以包括诸如可配置存储块和可配置处理块的专用块。 这种专用块可以由时钟信号控制，并以单数据速率或双数据速率运行。 例如，可配置的存储块可以被配置为使用双数据速率通信方案或单个数据速率通信方案来与其他块通信数据。 可配置处理块可以被配置为以双数据速率或单个数据速率处理数据。 此外，包括累加器电路的可配置处理块可以被配置为以单数据速率或双倍数据速率执行一次累加。 这种可配置处理块还可以被配置为以单个数据速率执行两次累加。

公开(公告)号：US09768783B1

公开(公告)日：2017-09-19

申请号：US15183457

申请日：2016-06-15

Applicant: Altera Corporation

Inventor： Herman Schmit ,  Jiefan Zhang

IPC: H03K19/177 ,  H03K19/173 ,  G11C7/22 ,  G11C7/10

CPC classification number: H03K19/1737 ,  G11C7/10 ,  G11C7/1045 ,  G11C7/106 ,  G11C7/22 ,  H03K3/02 ,  H03K19/173 ,  H03K19/17736 ,  H03K19/1776

Abstract: Integrated circuits such as application specific circuits or programmable logic devices may include specialized blocks such as configurable storage blocks and configurable processing blocks. Such specialized blocks may be controlled by clock signals and operated at single data rate or at double data rate. For instance, configurable storage blocks may be configured to use a double data rate communications scheme or a single data rate communication scheme to communicate data with other blocks. Configurable processing blocks may be configured to process data at a double data rate or a single data rate. Furthermore, configurable processing blocks that include accumulator circuitry may be configured to perform one accumulation at a single data rate or at a double data rate. Such configurable processing blocks may also be configured to perform two accumulations at a single data rate.

公开(公告)号：US09489175B2

公开(公告)日：2016-11-08

申请号：US14311359

申请日：2014-06-23

Applicant: Altera Corporation

Inventor： Herman Schmit ,  Jason Redgrave

IPC: H03K19/173 ,  G06F7/506

CPC classification number: G06F7/506 ,  G06F2207/3868 ,  H03K19/173

Abstract: Some embodiments provide a configurable IC that includes several configurable logic circuits, where the logic circuits include several sets of associated configurable logic circuits. For each several sets of associated configurable logic circuits, the reconfigurable IC also includes a carry circuit for performing up to N carry operations sequentially, wherein N is greater than two.

Abstract translation: 一些实施例提供了包括若干可配置逻辑电路的可配置IC，其中逻辑电路包括若干组相关联的可配置逻辑电路。 对于每组几组相关联的可配置逻辑电路，可重新配置的IC还包括一个执行多达N个进位操作的进位电路，其中N大于2。

公开(公告)号：US09385725B2

公开(公告)日：2016-07-05

申请号：US14664755

申请日：2015-03-20

Applicant: Altera Corporation

Inventor： Brad Hutchings ,  Jason Redgrave ,  Teju Khubchandani ,  Herman Schmit ,  Steven Teig

IPC: G06F7/38 ,  H03K19/173 ,  H03K19/177

CPC classification number: H03K19/1731 ,  H03K19/177 ,  H03K19/17704 ,  H03K19/17736 ,  H03K19/17748 ,  H03K19/17756 ,  H03K19/17764

Abstract: Some embodiments of the invention provide a configurable integrated circuit (IC) that has several configurable circuits for configurably performing different operations. During the operation of the IC, each particular configurable circuit performs a particular operation that is specified by a particular configuration data set for the particular configurable circuit. While the IC operates and a first set of configurable circuits performs a first set of operations, configuration data is loaded from the outside of the IC for configuring a second set of configurable circuits. In some embodiments, the configurable IC includes a configuration network for rapid loading configuration data in the IC from outside of the IC. In some of these embodiments, the configuration network is a pipelined network. Also, the IC of some embodiments includes a configuration controller for retrieving configuration data from outside of the IC, formulating configuration data sets, and routing the configuration data sets to the second set of configurable circuits over the configuration network.

公开(公告)号：US09197531B1

公开(公告)日：2015-11-24

申请号：US13764614

申请日：2013-02-11

Applicant: ALTERA CORPORATION

Inventor： David W. Mendel ,  Herman Schmit

IPC: H04W24/00 ,  H04L12/26

CPC classification number: H04L43/106 ,  H04L43/0858

Abstract: One embodiment relates to a method of determining an arrival time of a data packet which has data striped across a plurality of lanes of a multi-lane link. Word arrival times for a subset of the words of the data packet are determined, each word arrival time corresponding to an arrival time of a word of the data packet at an individual lane of the multi-lane link. The arrival time of the data packet is determined using the word arrival times for the subset of words. Another embodiment relates to a method of determining an arrival time of a data packet which uses a measure of average fullness for a set of the FIFO buffers. Other embodiments and features are also disclosed.

Abstract translation: 一个实施例涉及一种确定数据分组的到达时间的方法，该数据分组具有跨多通道链路的多个通道的条带。 确定数据包的字的子集的字到达时间，每个字到达时间对应于多车道链路的单独车道处的数据包的字的到达时间。 数据包的到达时间是使用单词的子集的字到达时间来确定的。 另一个实施例涉及一种确定数据分组的到达时间的方法，该数据分组使用一组FIFO缓冲器的平均饱和度测量。 还公开了其它实施例和特征。

公开(公告)号：US20180109262A1

公开(公告)日：2018-04-19

申请号：US15666293

申请日：2017-08-01

Applicant: Altera Corporation

Inventor： Andy Lee ,  Herman Schmit

IPC: H03K19/177

CPC classification number: H03K19/17724 ,  H03K19/00315 ,  H03K19/17764

Abstract: An integrated circuit formed using a semiconductor substrate may include a logic circuit and a switch circuit, whereby the logic circuit operates at a first power supply voltage and the switch circuit operates at a second power supply voltage that is greater than the first power supply voltage. The logic circuit may be formed within a first triple well structure within the semiconductor substrate and is supplied with a first bias voltage. The switch circuit may be formed within a second triple well structure that is electrically isolated from the first triple well structure within the semiconductor substrate and is supplied with a second bias voltage. The switch circuit may receive a control signal that controls the first bias voltage and the second power supply voltage to turn off a transistor in the logic circuit during a programming operation of the integrated circuit.