公开(公告)号：US20180081696A1

公开(公告)日：2018-03-22

申请号：US15273321

申请日：2016-09-22

Applicant: Altera Corporation

Inventor： Paul Kim ,  Alfredo de la Cruz ,  Gary Brian Wallichs ,  Yi Peng

IPC: G06F9/44 ,  G06F17/50 ,  G11C7/10 ,  G06F13/16 ,  G11C5/14 ,  G06F13/40

CPC classification number: G06F13/4068 ,  G06F9/4401 ,  G06F9/4411 ,  G06F9/4416 ,  G06F13/1689 ,  G06F13/4027 ,  G06F17/505 ,  G06F17/5072 ,  G06F17/5077 ,  G06F2217/84

Abstract: Integrated circuits may have programmable logic circuitry and hard-coded circuitry. The hard-coded circuitry may include data circuitry, a processor, and memory. As the hard-coded circuitry has a limited capacity, a portion of the programmable logic circuitry may be configured using configuration data to serve as expanded soft-coded memory for the hard-coded processor. Instructions for controlling settings of the data circuitry may be stored on the hard-coded and soft-coded memory. An additional portion of the programmable logic circuitry may be configured using the configuration data to serve as a soft-coded processor that executes the instructions stored on the soft-coded memory. Use of the soft-coded processor and/or expanded soft-coded memory may allow for more advanced algorithms for initialization and calibration of the data circuitry than when only hard-coded memory is used and may allow for updated processor circuitry to be implemented.

公开(公告)号：US20240126960A1

公开(公告)日：2024-04-18

申请号：US18398699

申请日：2023-12-28

Applicant: Altera Corporation

Inventor： Yi Peng ,  Nathan Edward Krueger ,  Krishna Kumar Nagar ,  Brandon Lewis Gordon

IPC: G06F30/31 ,  G06F30/27 ,  G06F30/34

CPC classification number: G06F30/31 ,  G06F30/27 ,  G06F30/34 ,  G06F2111/20

Abstract: Systems and methods may provide recommendations for a circuit design based on components of the circuit and machine-learning techniques. For example, a system may include a processor-based device storing or accessing a computer-aided design application for an integrated circuit, where the computer-aided design application, when executed by the processor-based device, causes acts to be performed including receiving an indication of a first selected component from a library for a design for the integrated circuit, retrieving one or more suggested components from the library based at least in part on the first selected component, and populating a user interface with the first selected component and a first suggested component of the one or more suggested components for display on the processor-based device.

公开(公告)号：US09203408B1

公开(公告)日：2015-12-01

申请号：US14245291

申请日：2014-04-04

Applicant: Altera Corporation

Inventor： Yi Peng ,  Kenton Orthner

IPC: H03K19/173 ,  H03K19/177 ,  H03K19/003

CPC classification number: H03K19/003 ,  H03K19/17756 ,  H03K19/1776

Abstract: Integrated circuits may include embedded logic analyzer circuitry that monitors and stores data received from logic circuitry. The logic analyzer circuitry may include storage circuitry and logic analyzer control circuitry that controls the storage circuitry. The control circuitry may include trigger condition circuitry that compares the data to a trigger condition. When the data satisfies the trigger condition, the storage circuitry may stop storing the data and stored data may be conveyed to fault detection circuitry for debugging the design of the logic circuitry. The integrated circuit may include programmable memory elements that can be loaded with configuration data. The logic analyzer circuitry may include partial-reconfiguration control circuitry that reconfigures the control circuitry without reconfiguring other portions of the integrated circuit. The partial-reconfiguration control circuitry may, for example, update the trigger condition by reconfiguring the control circuitry while the rest of the integrated circuit continues to operate normally.

Abstract translation: 集成电路可以包括监视和存储从逻辑电路接收的数据的嵌入式逻辑分析器电路。 逻辑分析器电路可以包括控制存储电路的存储电路和逻辑分析仪控制电路。 控制电路可以包括将数据与触发条件进行比较的触发条件电路。 当数据满足触发条件时，存储电路可能会停止存储数据，并将存储的数据传送到故障检测电路，以调试逻辑电路的设计。 集成电路可以包括可以加载配置数据的可编程存储器元件。 逻辑分析器电路可以包括部分重新配置控制电路，其重新配置控制电路，而不重新配置集成电路的其他部分。 例如，部分重新配置控制电路可以通过重新配置控制电路来更新触发条件，同时集成电路的其余部分继续正常工作。

公开(公告)号：US09298865B1

公开(公告)日：2016-03-29

申请号：US14220926

申请日：2014-03-20

Applicant: Altera Corporation

Inventor： Yi Peng

IPC: G06F17/50

CPC classification number: G06F17/5022 ,  G06F17/5027

Abstract: Techniques and mechanisms debug a device implementing an optimized design using a pre-optimized design simulation. For example, data indicating interconnect in a pre-optimized design to simulate may be received. A node in common between the pre-optimized design and an optimized design may be identified. A tap at the output of the node in the optimized design may be inserted for providing data for the simulation.

Abstract translation: 技术和机制使用预优化设计模拟来调试实现优化设计的设备。 例如，可以接收指示预先优化的设计中的互连以进行模拟的数据。 可以识别预优化设计和优化设计之间共同的节点。 可以插入优化设计中节点输出端的抽头，以提供模拟数据。

公开(公告)号：US10509757B2

公开(公告)日：2019-12-17

申请号：US15273321

申请日：2016-09-22

Applicant: Altera Corporation

Inventor： Paul Kim ,  Alfredo de la Cruz ,  Gary Brian Wallichs ,  Yi Peng

IPC: G06F1/24 ,  G06F13/40 ,  G06F17/50 ,  G06F13/16 ,  G06F9/4401

Abstract: Integrated circuits may have programmable logic circuitry and hard-coded circuitry. The hard-coded circuitry may include data circuitry, a processor, and memory. As the hard-coded circuitry has a limited capacity, a portion of the programmable logic circuitry may be configured using configuration data to serve as expanded soft-coded memory for the hard-coded processor. Instructions for controlling settings of the data circuitry may be stored on the hard-coded and soft-coded memory. An additional portion of the programmable logic circuitry may be configured using the configuration data to serve as a soft-coded processor that executes the instructions stored on the soft-coded memory. Use of the soft-coded processor and/or expanded soft-coded memory may allow for more advanced algorithms for initialization and calibration of the data circuitry than when only hard-coded memory is used and may allow for updated processor circuitry to be implemented.

公开(公告)号：US09584130B1

公开(公告)日：2017-02-28

申请号：US15164503

申请日：2016-05-25

Applicant: Altera Corporation

Inventor： Scott J. Weber ,  Sean R. Atsatt ,  Yi Peng

IPC: H03K19/173 ,  H03K19/177 ,  H03K19/003 ,  G06F17/50

CPC classification number: H03K19/17756 ,  H03K19/003 ,  H03K19/17736

Abstract: Systems and methods are provided for coordinating the partial reconfiguration of a region of a configurable device (e.g., a SDM/CNoC/LSM system or device) through an interface that coordinates the stopping of the current persona in that region, the resetting of the new current persona, and the starting of the new persona in a manner that does not corrupt the memory of the affected region. The interface further provides signaling that the static region can use to protect itself during the partial reconfiguration, and disallows multiple partial reconfigurations of the same region at the same time.

Abstract translation: 提供了系统和方法，用于通过协调停止该区域中的当前角色的接口来协调可配置设备（例如，SDM / CNoC / LSM系统或设备）的区域的部分重新配置，重置新的 目前的角色，以及不损害受影响地区记忆的新角色的开始。 该接口还提供静态区域可用于在部分重新配置期间保护自身的信令，并且不允许同时对相同区域进行多个部分重新配置。

公开(公告)号：US10394990B1

公开(公告)日：2019-08-27

申请号：US15277356

申请日：2016-09-27

Applicant: Altera Corporation

Inventor： Kalen Brunham ,  Kevin Nealis ,  Yi Peng ,  Scott Weber

IPC: G06F17/50

Abstract: Devices and methods for initializing one or more registers of a programmable integrated circuit (IC) to store an initial condition value are provided. A first bitstream that programs the region of the IC to supply the initial condition value to the one or more registers is first programmed on the IC. Then, once the registers are initialized with the initial condition value, a second bitstream is subsequently programmed to the region of the IC to supply values associated with a function of the design to the one or more registers.