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1.发明申请公开(公告)号：US20150180501A1
公开(公告)日：2015-06-25
申请号：US14135198
申请日：2013-12-19
Applicant: Analog Devices, Inc.
Inventor： Matthew Louis Courcy , Martin Clara , Gabriele Manganaro , Gil Engel , Lawrence A. Singer
IPC: H03M1/74
CPC classification number: H03M1/747 , H03K17/162 , H03K17/693 , H03M1/068 , H03M1/66 , H03M1/742 , H03M1/745
Abstract: The present disclosure provides embodiments of an improved current steering switching element for use in a digital to analog (DAC) converter. Typically, each current steering switching element in the DAC converter provides a varying set of currents for converting a digital input signal. Generally, the switches and drivers in the current steering switching elements are scaled down proportionally to the current being provided by the current steering switching element according to a ratio as less and less current is being driven by the switching element in order to overcome timing errors. However, device sizes are limited by the production process. When a switch is not scaled proportionally to the current, settling timing errors are present and affects the performance of the DAC. The improved current steering switching element alleviates this issue of timing errors by replacing the single switch with two complementary current steering switches.
Abstract translation: 本公开提供了用于在数模转换器（DAC）中使用的改进的电流转向开关元件的实施例。 通常，DAC转换器中的每个电流转向开关元件提供用于转换数字输入信号的变化的电流组。 通常，当前转向开关元件中的开关和驱动器按照由当前转向开关元件提供的电流按比例按比例缩小，因为越来越少的电流被开关元件驱动以克服定时误差。 但是，设备尺寸受到生产过程的限制。 当开关未按比例与当前的比例缩放时，存在稳定的定时误差并影响DAC的性能。 改进的电流转向开关元件通过用两个互补电流转向开关替换单个开关来减轻定时误差的这个问题。
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公开(公告)号：US09871504B2
公开(公告)日：2018-01-16
申请号：US15045059
申请日：2016-02-16
Applicant: ANALOG DEVICES, INC.
Inventor： Martin Clara , Gil Engel
CPC classification number: H03K5/13 , H03K2005/00286 , H03M1/06 , H03M1/1061 , H03M1/1215 , H03M1/662
Abstract: Differential clock phase imbalance can produce undesirable spurious content at a digital to analog converter output, or interleaving spurs on an analog-to-digital converter output spectrum, or more generally, in interleaving circuit architectures that depend on rising and falling edges of a differential input clock for triggering digital-to-analog conversion or analog-to-digital conversion. A differential phase adjustment approach measures for the phase imbalance and corrects the differential clock input signals used for generating clock signals which drive the digital-to-analog converter or the analog-to-digital converter. The approach can reduce or eliminate this phase imbalance, thereby reducing detrimental effects due to phase imbalance or differential clock skew.
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公开(公告)号：US09887552B2
公开(公告)日：2018-02-06
申请号：US13829889
申请日：2013-03-14
Applicant: ANALOG DEVICES, INC.
Inventor： Gil Engel , Steven C Rose , Matthew Louis Courcy
CPC classification number: H02J4/00 , H03M1/1009 , H03M1/121 , H03M1/662 , H03M1/742 , Y10T307/492
Abstract: Embodiments of the present invention may provide non-invasive techniques for adjusting timing in multistage circuit systems. A multistage circuit system according to embodiments of the present invention may include a plurality of circuit stages coupled to signal lines that carry signals. The system may also include a plurality of load circuits, one provided in for each circuit stage. The load circuits may have inputs coupled to the signal lines that carry the input signals. Each load circuit may include a current source programmable independently of the other load circuits that propagates current through an input transistor in the respective load circuit that receives the signal. The current propagating through the input transistor may provide a load on the corresponding signal line, allowing fine timing adjustment for each circuit stage.
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Patent Agency Ranking
公开(公告)号：US10291248B2
公开(公告)日：2019-05-14
申请号：US15950436
申请日：2018-04-11
Applicant: Analog Devices, Inc.
Inventor： Gil Engel , Shawn S. Kuo , Steven C. Rose
Abstract: A time-interleaved digital-to-analog converter (DAC) uses M DAC cores to convert a digital input signal whose digital input words are spread to different DAC cores to produce a final analog outputs. The M DAC cores, operating in a time-interleaved fashion, can increase the sampling rate several times compared to the sampling rate of just one DAC. However, sequential time-interleaving DAC cores often exhibit undesirable spurs at the output. To spread those spurs to the noise floor, the time-interleaving DAC cores can be selected at a pseudo randomized manner or in a specific manner which can break up the sequential or periodic manner of selecting the DAC cores.
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公开(公告)号：US09584151B1
公开(公告)日：2017-02-28
申请号：US15058008
申请日：2016-03-01
Applicant: ANALOG DEVICES, INC.
Inventor： Gabriele Manganaro , Gil Engel
IPC: H03M1/66
CPC classification number: H03M1/0863 , H03M1/0673 , H03M1/0678 , H03M1/742
Abstract: Reducing distortions in a digital-to-analog converter is a challenge for circuit designers. For current steering digital-to-analog converters (DACs), a quad switching scheme has been used to remove code-dependent glitching which is otherwise present in dual switching schemes. However, due to various impairments in the circuit, e.g., mismatches in the transistors, some code-dependent distortions remain even when a quad switching scheme is implemented. To address this issue, the quad switching scheme can be randomized to improve dynamic linearity while relaxing driving circuitry design and power constraints. Advantageously, randomization reduces the code dependency of the distortions and makes the distortions appear more noise-like at the output of the DAC.
Abstract translation: 降低数模转换器的失真是电路设计人员面临的挑战。 对于当前的转向数模转换器（DAC），四路交换方案已被用于消除以双重切换方案存在的代码相关的毛刺。 然而，由于电路中的各种损伤，例如晶体管中的失配，即使实现四通道交换方案，仍然保留一些代码相关的失真。 为了解决这个问题，四方切换方案可以被随机化以改善动态线性度，同时放松驱动电路设计和功率限制。 有利的是，随机化降低了失真的代码依赖性，并且使得在DAC的输出处出现类似于失真的失真。
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公开(公告)号：US09118346B2
公开(公告)日：2015-08-25
申请号：US14135198
申请日：2013-12-19
Applicant: ANALOG DEVICES, INC.
Inventor： Matthew Louis Courcy , Martin Clara , Gabriele Manganaro , Gil Engel , Lawrence A. Singer
CPC classification number: H03M1/747 , H03K17/162 , H03K17/693 , H03M1/068 , H03M1/66 , H03M1/742 , H03M1/745
Abstract: The present disclosure provides embodiments of an improved current steering switching element for use in a digital to analog (DAC) converter. Typically, each current steering switching element in the DAC converter provides a varying set of currents for converting a digital input signal. Generally, the switches and drivers in the current steering switching elements are scaled down proportionally to the current being provided by the current steering switching element according to a ratio as less and less current is being driven by the switching element in order to overcome timing errors. However, device sizes are limited by the production process. When a switch is not scaled proportionally to the current, settling timing errors are present and affects the performance of the DAC. The improved current steering switching element alleviates this issue of timing errors by replacing the single switch with two complementary current steering switches.
Abstract translation: 本公开提供了用于在数模转换器（DAC）中使用的改进的电流转向开关元件的实施例。 通常，DAC转换器中的每个电流转向开关元件提供用于转换数字输入信号的变化的电流组。 通常，当前转向开关元件中的开关和驱动器按照由当前转向开关元件提供的电流按比例按比例缩小，因为越来越少的电流被开关元件驱动以克服定时误差。 但是，设备尺寸受到生产过程的限制。 当开关未按比例与当前的比例缩放时，存在稳定的定时误差并影响DAC的性能。 改进的电流转向开关元件通过用两个互补电流转向开关替换单个开关来减轻定时误差的这个问题。
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公开(公告)号：US20230275596A1
公开(公告)日：2023-08-31
申请号：US18171197
申请日：2023-02-17
Applicant: Analog Devices, Inc.
Inventor： Gil Engel , Paul S. Wilkins
IPC: H03M1/10
CPC classification number: H03M1/1009
Abstract: Techniques that enable calibration of digital-to-analog Converters (DACs) with minimal processing overhead. A single frequency bin can be used to calibrate errors between bits. A low frequency feedback path can be included into a low frequency low power ADC to determine the error signal that exists in the calibration bin. The bits are calibrated when this error signal is minimized. The calibration techniques described provide an extremely efficient and optimal calibration at the DAC output of both static and dynamic errors.
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公开(公告)号：US09966969B1
公开(公告)日：2018-05-08
申请号：US15490762
申请日：2017-04-18
Applicant: Analog Devices, Inc.
Inventor： Gil Engel , Shawn S. Kuo , Steven C. Rose
CPC classification number: H03M1/662 , H03M1/0673 , H03M1/1215 , H03M1/66
Abstract: A time-interleaved digital-to-analog converter (DAC) uses M DAC cores to convert a digital input signal whose digital input words are spread to different DAC cores to produce a final analog outputs. The M DAC cores, operating in a time-interleaved fashion, can increase the sampling rate several times compared to the sampling rate of just one DAC. However, sequential time-interleaving DAC cores often exhibit undesirable spurs at the output. To spread those spurs to the noise floor, the time-interleaving DAC cores can be selected at a pseudo randomized manner or in a specific manner which can break up the sequential or periodic manner of selecting the DAC cores.
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