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公开(公告)号：US10305495B2
公开(公告)日：2019-05-28
申请号：US15287435
申请日：2016-10-06
Applicant: Analog Devices, Inc.
Inventor： John Kevin Behel , Reuben Pascal Nelson , Matthew D. McShea , Matthew Louis Courcy , Kenny Gentile , Carroll C. Speir
Abstract: Aspects of this disclosure relate to adjusting a phase of a clock signal provided to a device based on a feedback signal from the device. The feedback signal can provide phase information associated with the device and/or other information associated with the device, such as temperature information. A feedback signal processor can compute a phase control signal based on the feedback signal. The phase control signal can be used to adjust the phase of the clock signal. By adjusting the phase of one or more clock signals, several devices, such as data converters, can be synchronized.
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公开(公告)号：US09564913B1
公开(公告)日：2017-02-07
申请号：US15064799
申请日：2016-03-09
Applicant: ANALOG DEVICES, INC.
Inventor： Matthew Louis Courcy
CPC classification number: H03M1/0836 , G06F1/04 , H03L7/0891 , H03M1/0607 , H03M1/662 , H04L7/033
Abstract: Disclosed systems include a clock-multiplying phase locked loop (PLL) generating a clock signal for a DAC comprising a plurality of DAC cells, the systems configured to control that a phase of the DAC output has a predefined relation to a phase of a PLL input reference clock. An exemplary system incorporates an auxiliary DAC cell implemented as a replica of one of the DAC cells of the DAC and operation of the DAC and the auxiliary DAC cell is timed with the same clock signal generated by the PLL, so that outputs of the auxiliary cell and the DAC are phase synchronized by design. The system is configured to ensure that a phase of the auxiliary DAC cell output is related to the phase of the PLL reference clock, which results in a phase of the DAC output also being related to the phase of the PLL reference clock.
Abstract translation: 公开的系统包括产生包括多个DAC单元的DAC的时钟信号的时钟倍增锁相环（PLL），该系统被配置为控制DAC输出的相位与PLL输入的相位具有预定的关系 参考时钟。 示例性系统包括实现为DAC的DAC单元之一的副本的辅助DAC单元，并且DAC和辅助DAC单元的操作与由PLL产生的相同的时钟信号定时，使得辅助单元的输出 并且DAC通过设计进行相位同步。 该系统被配置为确保辅助DAC单元输出的相位与PLL参考时钟的相位相关，这导致DAC输出的相位也与PLL参考时钟的相位相关。
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3.发明申请公开(公告)号：US20150180501A1
公开(公告)日：2015-06-25
申请号：US14135198
申请日：2013-12-19
Applicant: Analog Devices, Inc.
Inventor： Matthew Louis Courcy , Martin Clara , Gabriele Manganaro , Gil Engel , Lawrence A. Singer
IPC: H03M1/74
CPC classification number: H03M1/747 , H03K17/162 , H03K17/693 , H03M1/068 , H03M1/66 , H03M1/742 , H03M1/745
Abstract: The present disclosure provides embodiments of an improved current steering switching element for use in a digital to analog (DAC) converter. Typically, each current steering switching element in the DAC converter provides a varying set of currents for converting a digital input signal. Generally, the switches and drivers in the current steering switching elements are scaled down proportionally to the current being provided by the current steering switching element according to a ratio as less and less current is being driven by the switching element in order to overcome timing errors. However, device sizes are limited by the production process. When a switch is not scaled proportionally to the current, settling timing errors are present and affects the performance of the DAC. The improved current steering switching element alleviates this issue of timing errors by replacing the single switch with two complementary current steering switches.
Abstract translation: 本公开提供了用于在数模转换器（DAC）中使用的改进的电流转向开关元件的实施例。 通常，DAC转换器中的每个电流转向开关元件提供用于转换数字输入信号的变化的电流组。 通常，当前转向开关元件中的开关和驱动器按照由当前转向开关元件提供的电流按比例按比例缩小，因为越来越少的电流被开关元件驱动以克服定时误差。 但是，设备尺寸受到生产过程的限制。 当开关未按比例与当前的比例缩放时，存在稳定的定时误差并影响DAC的性能。 改进的电流转向开关元件通过用两个互补电流转向开关替换单个开关来减轻定时误差的这个问题。
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Patent Agency Ranking
公开(公告)号：US10727842B2
公开(公告)日：2020-07-28
申请号：US16418777
申请日：2019-05-21
Applicant: Analog Devices, Inc.
Inventor： John Kevin Behel , Kenny Gentile , Carroll C. Speir , Matthew D. McShea , Matthew Louis Courcy , Reuben Pascal Nelson
Abstract: Aspects of this disclosure relate to adjusting a phase of a clock signal provided to a device based on a feedback signal from the device. The feedback signal can provide phase information associated with the device and/or other information associated with the device, such as temperature information. A feedback signal processor can compute a phase control signal based on the feedback signal. The phase control signal can be used to adjust the phase of the clock signal. By adjusting the phase of one or more clock signals, several devices, such as data converters, can be synchronized.
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公开(公告)号：US20190341922A1
公开(公告)日：2019-11-07
申请号：US16418777
申请日：2019-05-21
Applicant: Analog Devices, Inc.
Inventor： John Kevin Behel , Kenny Gentile , Carroll C. Speir , Matthew D. McShea , Matthew Louis Courcy , Reuben Pascal Nelson
Abstract: Aspects of this disclosure relate to adjusting a phase of a clock signal provided to a device based on a feedback signal from the device. The feedback signal can provide phase information associated with the device and/or other information associated with the device, such as temperature information. A feedback signal processor can compute a phase control signal based on the feedback signal. The phase control signal can be used to adjust the phase of the clock signal. By adjusting the phase of one or more clock signals, several devices, such as data converters, can be synchronized.
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公开(公告)号：US09118346B2
公开(公告)日：2015-08-25
申请号：US14135198
申请日：2013-12-19
Applicant: ANALOG DEVICES, INC.
Inventor： Matthew Louis Courcy , Martin Clara , Gabriele Manganaro , Gil Engel , Lawrence A. Singer
CPC classification number: H03M1/747 , H03K17/162 , H03K17/693 , H03M1/068 , H03M1/66 , H03M1/742 , H03M1/745
Abstract: The present disclosure provides embodiments of an improved current steering switching element for use in a digital to analog (DAC) converter. Typically, each current steering switching element in the DAC converter provides a varying set of currents for converting a digital input signal. Generally, the switches and drivers in the current steering switching elements are scaled down proportionally to the current being provided by the current steering switching element according to a ratio as less and less current is being driven by the switching element in order to overcome timing errors. However, device sizes are limited by the production process. When a switch is not scaled proportionally to the current, settling timing errors are present and affects the performance of the DAC. The improved current steering switching element alleviates this issue of timing errors by replacing the single switch with two complementary current steering switches.
Abstract translation: 本公开提供了用于在数模转换器（DAC）中使用的改进的电流转向开关元件的实施例。 通常，DAC转换器中的每个电流转向开关元件提供用于转换数字输入信号的变化的电流组。 通常，当前转向开关元件中的开关和驱动器按照由当前转向开关元件提供的电流按比例按比例缩小，因为越来越少的电流被开关元件驱动以克服定时误差。 但是，设备尺寸受到生产过程的限制。 当开关未按比例与当前的比例缩放时，存在稳定的定时误差并影响DAC的性能。 改进的电流转向开关元件通过用两个互补电流转向开关替换单个开关来减轻定时误差的这个问题。
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公开(公告)号：US20180102779A1
公开(公告)日：2018-04-12
申请号：US15287435
申请日：2016-10-06
Applicant: Analog Devices, Inc.
Inventor： John Kevin Behel , Reuben Pascal Nelson , Matthew D. McShea , Matthew Louis Courcy , Kenny Gentile , Carroll C. Speir
CPC classification number: H03L7/087 , H03K5/1508 , H03L7/06 , H03L7/0814 , H04L7/02
Abstract: Aspects of this disclosure relate to adjusting a phase of a clock signal provided to a device based on a feedback signal from the device. The feedback signal can provide phase information associated with the device and/or other information associated with the device, such as temperature information. A feedback signal processor can compute a phase control signal based on the feedback signal. The phase control signal can be used to adjust the phase of the clock signal. By adjusting the phase of one or more clock signals, several devices, such as data converters, can be synchronized.
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公开(公告)号：US09887552B2
公开(公告)日：2018-02-06
申请号：US13829889
申请日：2013-03-14
Applicant: ANALOG DEVICES, INC.
Inventor： Gil Engel , Steven C Rose , Matthew Louis Courcy
CPC classification number: H02J4/00 , H03M1/1009 , H03M1/121 , H03M1/662 , H03M1/742 , Y10T307/492
Abstract: Embodiments of the present invention may provide non-invasive techniques for adjusting timing in multistage circuit systems. A multistage circuit system according to embodiments of the present invention may include a plurality of circuit stages coupled to signal lines that carry signals. The system may also include a plurality of load circuits, one provided in for each circuit stage. The load circuits may have inputs coupled to the signal lines that carry the input signals. Each load circuit may include a current source programmable independently of the other load circuits that propagates current through an input transistor in the respective load circuit that receives the signal. The current propagating through the input transistor may provide a load on the corresponding signal line, allowing fine timing adjustment for each circuit stage.
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