Enhanced smoothness digital-to-analog converter interpolation systems and methods

    公开(公告)号:US11651719B2

    公开(公告)日:2023-05-16

    申请号:US17376131

    申请日:2021-07-14

    Applicant: Apple Inc.

    Abstract: An electronic device may include an electronic display panel having multiple display pixels for displaying an image based on analog voltage signals. The electronic device may also include interpolation circuitry to generate the analog voltage signals based on digital image data corresponding to the image. The interpolation circuitry may also receive analog reference voltages and interpolate between sets of the analog reference voltages to generate intermediate voltages, which may be a part of the analog voltage signals. Interpolating between the sets analog reference voltages may include performing a first level interpolation of a first set of the analog reference voltages to generate a first intermediate voltage and performing a second level interpolation of a second set of the analog reference voltages to generate a second intermediate voltage, wherein the first level interpolation is different from the second level interpolation.

    Time-interleaved source driver for display devices

    公开(公告)号:US10438535B2

    公开(公告)日:2019-10-08

    申请号:US15697172

    申请日:2017-09-06

    Applicant: Apple Inc.

    Abstract: A display device may include a plurality of pixels that display image data on a display, a digital-to-analog converter that outputs a voltage that corresponds to a luminance value to be depicted on a first pixel, and a circuit that amplifies the voltage and outputs an amplified voltage to the first pixel. The circuit may include a capacitor that receives the voltage via the digital-to-analog converter and an amplifier coupled to the capacitor. The amplifier generates the amplified voltage based on the voltage stored the capacitor. The circuit also include switches that couple a first terminal of the capacitor to an output of the amplifier during a first amount of time and couples a second terminal of the capacitor to the output of the amplifier after the first amount of time expires.

    Mitigation of power supply disturbance for wired-line transmitters

    公开(公告)号:US09715262B2

    公开(公告)日:2017-07-25

    申请号:US14471759

    申请日:2014-08-28

    Applicant: Apple Inc.

    CPC classification number: G06F1/266 H04L25/0286 H04L25/03

    Abstract: A wired-line transmitter may include architecture that provides control of the current profile during power-up and/or power-down of the transmitter. The current profile may include a sloped ramp up during power-up and/or a sloped ramp down during power-down. The sloped ramps of the current profile mitigate supply bouncing during power-up and/or power-down. Individual enable signals may be derived from an enable signal provided to the transmitter. These individual enable signals may be provided (or turned off) in a time delayed (e.g., staggered) manner to provide the sloped ramps for the current profile.

    AUTO-ZERO APPLIED BUFFER FOR DISPLAY CIRCUITRY

    公开(公告)号:US20210056904A1

    公开(公告)日:2021-02-25

    申请号:US16905895

    申请日:2020-06-18

    Applicant: Apple Inc.

    Abstract: A system includes a pixel that emits light based on a signal provided to the pixel. The system may also include a buffer circuit having a differential pair stage, a cascade stage, and an output stage. The differential pair stage may receive a common mode voltage signal via a first switch in response to the first switch receiving a first signal that causes the first switch to close. The differential pair stage may couple a capacitor to the output stage via a second switch that operate based on a second signal, such that the capacitor reduces an offset provided by one or more circuit components in the differential pair stage, the cascade stage, the output stage, or any combination thereof. The differential pair stage may output the common mode voltage to the pixel via the output stage in response to the first signal being present.

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