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公开(公告)号：US20170126133A1
公开(公告)日：2017-05-04
申请号：US15064395
申请日：2016-03-08
Applicant: Apple Inc.
Inventor： Zaohong Yang , Behzad Mohtashemi
IPC: H02M3/335
CPC classification number: H02M3/33507 , H02M3/33576 , H02M3/33592 , H02M2001/0067 , H02M2001/007 , H02M2001/0074 , H02M2001/0077
Abstract: This disclosure relates to power converters that are capable of providing smooth transitions between multiple output voltage levels. The converter's output may need to be changed from, e.g., 5V to 12V, 15V, or 20V—based on the charging device's request. By using improved power converter designs comprising both a flyback converter circuit and variable-frequency buck converter circuit that may each be selectively coupled to an output load, a more smooth, e.g., monotonous, transition between output voltage levels may be achieved. In particular, by varying the switching frequency of the buck converter in a controlled way, the output voltage of the power converter may rise monotonically during the transition between output voltage levels. According to some embodiments, once the output of the buck converter has reached its maximum value, the buck converter may be disabled, and the flyback converter may be enabled to begin supplying the output voltage to the load.
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公开(公告)号：US10855192B1
公开(公告)日：2020-12-01
申请号：US16538963
申请日：2019-08-13
Applicant: Apple Inc.
Inventor： Zaohong Yang , Marco A. Davila, Jr. , Joao L. Andres , Poornima Mazumdar , Bogdan T. Bucheru
Abstract: A transformer-based switching power converter can include a slew rate limiter coupled to the switching stage and configured to limit rate of change of voltage across one or more switching devices of the switching stage, thereby reducing voltage spikes appearing on the secondary winding. The slew rate limiter may be configured to selectively operate to limit rate of change of voltage across one or more switching devices of the switching stage during startup of the switching stage, upon waking from burst mode, or at any time when zero voltage switching of the one or more switching devices is unavailable. The slew rate limiter can include at least one circuit element configured to selectively alter a time constant of a gate drive circuit of at least one switching device in the switching stage to increase a turn-on transition time of the at least one switching device.
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公开(公告)号：US10320194B2
公开(公告)日：2019-06-11
申请号：US15850752
申请日：2017-12-21
Applicant: Apple Inc.
Inventor： Zaohong Yang , Bogdan T. Bucheru
Abstract: Disclosed herein are a system, method and non-transitory program storage device that are intended to provide a control system with quick response for a multi-level power converter. The control system may regulate an output voltage of the power converter based on one or more feedback signals. The feedback signals may be generated based on a differential between the output voltage and a reference voltage. The control system may further include one or more feed-forward signals representative of either the output voltage or transients of the output voltage. The control system may further include one or more switches in parallel with the one or more capacitors to selectively enable and/or disable direct feed-forward and capacitive feed-forward responsive to the output voltage at different levels.
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公开(公告)号：US09893628B2
公开(公告)日：2018-02-13
申请号：US15064395
申请日：2016-03-08
Applicant: Apple Inc.
Inventor： Zaohong Yang , Behzad Mohtashemi
CPC classification number: H02M3/33507 , H02M3/33576 , H02M3/33592 , H02M2001/0067 , H02M2001/007 , H02M2001/0074 , H02M2001/0077
Abstract: This disclosure relates to power converters that are capable of providing smooth transitions between multiple output voltage levels. The converter's output may need to be changed from, e.g., 5V to 12V, 15V, or 20V—based on the charging device's request. By using improved power converter designs comprising both a flyback converter circuit and variable-frequency buck converter circuit that may each be selectively coupled to an output load, a more smooth, e.g., monotonous, transition between output voltage levels may be achieved. In particular, by varying the switching frequency of the buck converter in a controlled way, the output voltage of the power converter may rise monotonically during the transition between output voltage levels. According to some embodiments, once the output of the buck converter has reached its maximum value, the buck converter may be disabled, and the flyback converter may be enabled to begin supplying the output voltage to the load.
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公开(公告)号：US20170093289A1
公开(公告)日：2017-03-30
申请号：US15177998
申请日：2016-06-09
Applicant: Apple Inc.
Inventor： Zaohong Yang
CPC classification number: H02M3/33507 , H02M3/33592 , Y02B70/1475
Abstract: This disclosure relates to flyback transformer-based power converters that are capable of providing multiple output voltage levels. With respect to USB-PD adapter design, the flyback converter's output may be changed from 12V to 20V—based on the charging device's request. By using a bias circuit that monitors an output voltage level of the flyback converter, a bias voltage for the bias circuit may be determined to improve efficiency of the flyback converter. Embodiments include a comparator, microcontroller or switches to compare output voltage levels and provide bias voltages to the bias circuit.
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Patent Agency Ranking
公开(公告)号：US20160094130A1
公开(公告)日：2016-03-31
申请号：US14498578
申请日：2014-09-26
Applicant: Apple Inc.
Inventor： Zaohong Yang
IPC: H02M3/335
CPC classification number: H02M3/33569 , H02M3/33561 , H02M2001/0054 , Y02B70/1433 , Y02B70/1491
Abstract: The disclosed embodiments present a flyback voltage converter that reduces switching losses in a primary-side switching transistor. This flyback converter includes a primary current path that feeds from an input power source into a voltage input of the flyback converter, then through a primary winding of a transformer and a primary transistor to a primary ground. It also includes a secondary current path that feeds from a secondary ground through a secondary winding of the transformer and a diode to a voltage output. During operation, the flyback converter toggles the primary transistor on and off to cause current to flow in an alternating fashion through the primary and secondary current paths. During this toggling process, before the primary transistor is turned on, a parasitic capacitance from the primary transistor is discharged into a reservoir capacitor. This charge is subsequently used to facilitate power efficiency in the flyback converter.
Abstract translation: 所公开的实施例提供了降低初级侧开关晶体管中的开关损耗的反激式电压转换器。 该反激式转换器包括从电源输入到反激式转换器的电压输入端的初级电流路径，然后通过变压器的初级绕组和初级晶体管馈送到主地。 它还包括一个次级电流通路，从二次接地通过变压器的次级绕组和二极管馈送到电压输出端。 在操作期间，反激转换器切换初级晶体管的导通和截止，以使电流以交替的方式通过初级和次级电流路径流动。 在该切换处理期间，在初级晶体管导通之前，来自初级晶体管的寄生电容被放电到储存电容器中。 随后，该电荷用于促进反激式转换器的功率效率。
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公开(公告)号：US09887630B2
公开(公告)日：2018-02-06
申请号：US15354705
申请日：2016-11-17
Applicant: Apple Inc.
Inventor： Bogdan T. Bucheru , Zaohong Yang
IPC: H02M3/335
CPC classification number: H02M3/33523 , H02M3/33507 , H02M3/33553 , H02M2001/0025
Abstract: This disclosure describes an AC/DC power converter that produces multiple output voltage levels. The AC/DC power converter may include a gain adjustment circuit. The gain adjustment circuit may adjust the gain of a feedback signal of the converter in accordance with the converter's output voltage level. The gain adjustment circuit provides sufficient gain and phase margins to the converter and thus enhances the converter's stability.
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公开(公告)号：US20160190948A1
公开(公告)日：2016-06-30
申请号：US14985040
申请日：2015-12-30
Applicant: Apple Inc.
Inventor： Zaohong Yang , Bharatkumar K. Patel , Bogdan T. Bucheru , Juan Carlos Pastrana
IPC: H02M3/335
CPC classification number: H02M3/33592 , H02M1/32 , H02M2001/0032 , H02M2001/0038 , H02M2001/0054 , Y02B70/1475 , Y02B70/1491 , Y02B70/16
Abstract: The disclosed embodiments provide a system that operates a flyback converter. During activation of a synchronous rectifier (SR) controller on a secondary side of the power converter, the system temporarily disables driving of a gate of a metal-oxide-semiconductor field-effect transistor (MOSFET) by the SR controller to enable synchronization of the SR controller to a switching frequency on a primary side of the power converter. After driving of the gate of the MOSFET by the SR controller has been disabled for a pre-specified period, the system enables driving of the gate of the MOSFET by the SR controller.
Abstract translation: 所公开的实施例提供了操作反激转换器的系统。 在功率转换器的次级侧激活同步整流器（SR）控制器期间，系统暂时禁止由SR控制器驱动金属氧化物半导体场效应晶体管（MOSFET）的栅极，以使得能够同步 SR控制器到功率转换器初级侧的开关频率。 在SR控制器驱动MOSFET的栅极已经被禁止预定的时间段之后，该系统能够通过SR控制器驱动MOSFET的栅极。
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公开(公告)号：US10418906B2
公开(公告)日：2019-09-17
申请号：US15177998
申请日：2016-06-09
Applicant: Apple Inc.
Inventor： Zaohong Yang
IPC: H02M3/335
Abstract: This disclosure relates to flyback transformer-based power converters that are capable of providing multiple output voltage levels. With respect to USB-PD adapter design, the flyback converter's output may be changed from 12V to 20V—based on the charging device's request. By using a bias circuit that monitors an output voltage level of the flyback converter, a bias voltage for the bias circuit may be determined to improve efficiency of the flyback converter. Embodiments include a comparator, microcontroller or switches to compare output voltage levels and provide bias voltages to the bias circuit.
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公开(公告)号：US20190074692A1
公开(公告)日：2019-03-07
申请号：US15850752
申请日：2017-12-21
Applicant: Apple Inc.
Inventor： Zaohong Yang , Bogdan T. Bucheru
Abstract: Disclosed herein are a system, method and non-transitory program storage device that are intended to provide a control system with quick response for a multi-level power converter. The control system may regulate an output voltage of the power converter based on one or more feedback signals. The feedback signals may be generated based on a differential between the output voltage and a reference voltage. The control system may further include one or more feed-forward signals representative of either the output voltage or transients of the output voltage. The control system may further include one or more switches in parallel with the one or more capacitors to selectively enable and/or disable direct feed-forward and capacitive feed-forward responsive to the output voltage at different levels.
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