公开(公告)号：US20240090213A1

公开(公告)日：2024-03-14

申请号：US18238954

申请日：2023-08-28

Applicant: Applied Materials, Inc.

Inventor： Jialiang WANG ,  Soonil LEE ,  Eswaranand VENKATASUBRAMANIAN ,  Chang Seok KANG ,  Sanjay G. KAMATH ,  Abhijit B. MALLICK ,  Srinivas GUGGILLA ,  Amy CHILD ,  Sung-Kwan KANG ,  Balasubramanian PRANATHARTHIHARAN

IPC: H10B41/35 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/67 ,  H10B43/10

CPC classification number: H10B41/35 ,  H01L21/02164 ,  H01L21/02274 ,  H01L21/3065 ,  H01L21/67063 ,  H10B43/10 ,  H10B80/00

Abstract: A method of forming a semiconductor memory device includes simultaneously filling a top portion of a first high aspect ratio (HAR) structure and a top portion a second HAR structure with a silicon-containing sacrificial layer by a cycle of a deposition process and an etch process, wherein the first HAR structure has a critical dimension (CD) of between 150 nm and 250 nm, and the second HAR structure has a CD of between 250 nm and 400 nm.