公开(公告)号：US20200251310A1

公开(公告)日：2020-08-06

申请号：US16748632

申请日：2020-01-21

Applicant: Applied Materials, Inc.

Inventor： Madhu Santosh Kumar MUTYALA ,  Sanjay G. KAMATH ,  Deenesh PADHI ,  Arkajit Roy BARMAN

IPC: H01J37/32 ,  H05B1/02 ,  H01L21/67

Abstract: Embodiments described herein relate to gas line systems with a multichannel splitter spool. In these embodiments, the gas line systems will include a first gas line that is configured to supply a first gas. The first gas line is coupled to a multichannel splitter spool with a plurality of second gas lines into which the first gas flows. Each gas line of the plurality of second gas lines will have a smaller volume than the volume of the first gas line. The smaller second gas lines will be wrapped by a heater jacket. Due to the smaller volume of the second gas lines, when the first gas is flowed through the second gas lines, the heater jacket will sufficiently heat the first gas, eliminating the condensation induced particle defects that occur in conventional gas line systems when the first gas meets with a second gas in the gas line system.

公开(公告)号：US20240282605A1

公开(公告)日：2024-08-22

申请号：US18172149

申请日：2023-02-21

Applicant: Applied Materials, Inc.

Inventor： Rupankar CHOUDHURY ,  Sanjay G. KAMATH ,  Sridhar BACHU

IPC: H01L21/67 ,  F24F13/14 ,  F24F13/32 ,  H01L21/673

CPC classification number: H01L21/6719 ,  F24F13/1413 ,  F24F13/1486 ,  F24F13/32 ,  H01L21/67383 ,  H01L21/67393

Abstract: An apparatus and system for minimizing particle return to the processing area of a processing chamber are disclosed herein. In one example, a particle shield for a semiconductor vacuum processing chamber includes an annular ring, a plurality of rib supports, and a plurality of louver fins. The annular ring has top surface, a bottom surface, and a plurality of cutaways. The top surface has an upper outer portion and a lower inner portion. The plurality of rib supports are disposed on and supported by the lower inner portion. The plurality of louver fins have a truncated conical shape, a bottom surface of the louver fins supported in a recess formed in a top surface of the rib supports. Each of the plurality of louver fins are disposed between adjacent concentric louver fins that have an outer diameter greater than an inner diameter of the outwardly adjacent louver fin.

公开(公告)号：US20230030436A1

公开(公告)日：2023-02-02

申请号：US17390151

申请日：2021-07-30

Applicant: Applied Materials, Inc.

Inventor： Jung Chan LEE ,  Mun Kyu PARK ,  Jun LEE ,  Euhngi LEE ,  Kyu-Ha SHIM ,  Deven Matthew Raj MITTAL ,  Sungho JO ,  Timothy MILLER ,  Jingmei LIANG ,  Praket Prakash JHA ,  Sanjay G. KAMATH

IPC: H01L21/02

Abstract: Embodiments of the present disclosure generally relate to methods for gap fill deposition and film densification on microelectronic devices. The method includes forming an oxide layer containing silicon oxide and having an initial wet etch rate (WER) over features disposed on the substrate, and exposing the oxide layer to a first plasma treatment to produce a treated oxide layer. The first plasma treatment includes generating a first plasma by a first RF source and directing the first plasma to the oxide layer by a DC bias. The method also includes exposing the treated oxide layer to a second plasma treatment to produce a densified oxide layer. The second plasma treatment includes generating a second plasma by top and side RF sources and directing the second plasma to the treated oxide layer without a bias. The densified oxide layer has a final WER of less than one-half of the initial WER.

公开(公告)号：US20190385844A1

公开(公告)日：2019-12-19

申请号：US16444865

申请日：2019-06-18

Applicant: Applied Materials, Inc.

Inventor： Vinayak Veer VATS ,  Hang YU ,  Deenesh PADHI ,  Changling LI ,  Gregory M. AMICO ,  Sanjay G. KAMATH

IPC: H01L21/02 ,  H01L21/3065

Abstract: Embodiments of the present disclosure relate to methods for in-situ deposition and treatment of a thin film for improved step coverage. In one embodiment, the method for processing a substrate is provided. The method includes forming a dielectric layer on patterned features of the substrate by exposing the substrate to a gas mixture of a first precursor and a second precursor simultaneously with plasma present in a process chamber, wherein the plasma is formed by a first pulsed RF power, exposing the dielectric layer to a first plasma treatment using a gas mixture of nitrogen and helium in the process chamber, and performing a plasma etch process by exposing the dielectric layer to a plasma formed from a gas mixture of a fluorine-containing precursor and a carrier gas, wherein the plasma is formed in the process chamber by a second pulsed RF power.

公开(公告)号：US20240404823A1

公开(公告)日：2024-12-05

申请号：US18803673

申请日：2024-08-13

Applicant: Applied Materials, Inc.

Inventor： Jung chan LEE ,  Mun Kyu PARK ,  Jun LEE ,  Euhngi LEE ,  Kyu-Ha SHIM ,  Deven Matthew Raj MITTAL ,  Sungho JO ,  Timothy MILLER ,  Jingmei LIANG ,  Praket Prakash JHA ,  Sanjay G. KAMATH

IPC: H01L21/02

Abstract: Embodiments of the present disclosure generally relate to methods for gap fill deposition and film densification on microelectronic devices. The method includes forming an oxide layer containing silicon oxide and having an initial wet etch rate (WER) over features disposed on the substrate, and exposing the oxide layer to a first plasma treatment to produce a treated oxide layer. The first plasma treatment includes generating a first plasma and directing the first plasma to the oxide layer. The method also includes exposing the treated oxide layer to a second plasma treatment to produce a densified oxide layer. The second plasma treatment includes generating a second plasma and directing the second plasma to the treated oxide layer. The densified oxide layer has a final WER of less than one-half of the initial WER.

公开(公告)号：US20240090213A1

公开(公告)日：2024-03-14

申请号：US18238954

申请日：2023-08-28

Applicant: Applied Materials, Inc.

Inventor： Jialiang WANG ,  Soonil LEE ,  Eswaranand VENKATASUBRAMANIAN ,  Chang Seok KANG ,  Sanjay G. KAMATH ,  Abhijit B. MALLICK ,  Srinivas GUGGILLA ,  Amy CHILD ,  Sung-Kwan KANG ,  Balasubramanian PRANATHARTHIHARAN

IPC: H10B41/35 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/67 ,  H10B43/10

CPC classification number: H10B41/35 ,  H01L21/02164 ,  H01L21/02274 ,  H01L21/3065 ,  H01L21/67063 ,  H10B43/10 ,  H10B80/00

Abstract: A method of forming a semiconductor memory device includes simultaneously filling a top portion of a first high aspect ratio (HAR) structure and a top portion a second HAR structure with a silicon-containing sacrificial layer by a cycle of a deposition process and an etch process, wherein the first HAR structure has a critical dimension (CD) of between 150 nm and 250 nm, and the second HAR structure has a CD of between 250 nm and 400 nm.