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公开(公告)号:US20220364229A1
公开(公告)日:2022-11-17
申请号:US17317565
申请日:2021-05-11
Applicant: Applied Materials, Inc.
Inventor: Tetsuya ISHIKAWA , Swaminathan T. SRINIVASAN , Matthias BAUER , Manjunath SUBBANNA , Ala MORADIAN , Kartik Bhupendra SHAH , Errol Antonio C SANCHEZ , Michael R. RICE , Peter REIMER , Marc SHULL
Abstract: Embodiments described herein include processes and apparatuses relate to epitaxial deposition. A method for epitaxially depositing a material is provided and includes positioning a substrate on a substrate support surface of a susceptor within a process volume of a chamber body, where the process volume contains upper and lower chamber regions. The method includes flowing a process gas containing one or more chemical precursors from an upper gas inlet on a first side of the chamber body, across the substrate, and to an upper gas outlet on a second side of the chamber body, flowing a purge gas from a lower gas inlet on the first side of the chamber body, across the lower surface of the susceptor, and to a lower gas outlet on the second side of the chamber body, and maintaining a pressure of the lower chamber region greater than a pressure of the upper chamber region.
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公开(公告)号:US20240337020A1
公开(公告)日:2024-10-10
申请号:US18747687
申请日:2024-06-19
Applicant: Applied Materials, Inc.
Inventor: Tetsuya ISHIKAWA , Swaminathan T. SRINIVASAN , Matthias BAUER , Ala MORADIAN , Manjunath SUBBANNA , Kartik Bhupendra SHAH , Errol Antonio C. SANCHEZ , Sohrab ZOKAEI , Michael R. RICE , Peter REIMER
IPC: C23C16/455 , B01J4/00 , C23C16/44
CPC classification number: C23C16/4558 , B01J4/005 , B01J4/008 , C23C16/4412 , C23C16/45587
Abstract: The present disclosure generally relates to gas inject apparatus for a process chamber for processing of semiconductor substrates. The gas inject apparatus include one or more gas injectors which are configured to be coupled to the process chamber. Each of the gas injectors are configured to receive a process gas and distribute the process gas across one or more gas outlets. The gas injectors include a plurality of pathways, a fin array, and a baffle array. The gas injectors are individually heated. A gas mixture assembly is also utilized to control the concentration of process gases flown into a process volume from each of the gas injectors. The gas mixture assembly enables the concentration as well as the flow rate of the process gases to be controlled.
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公开(公告)号:US20220364261A1
公开(公告)日:2022-11-17
申请号:US17317363
申请日:2021-05-11
Applicant: Applied Materials, Inc.
Inventor: Tetsuya ISHIKAWA , Swaminathan T. SRINIVASAN , Kartik Bhupendra SHAH , Ala MORADIAN , Manjunath SUBBANNA , Matthias BAUER , Peter REIMER , Michael R. RICE
IPC: C30B25/08 , C30B25/12 , C30B25/14 , C30B25/10 , C23C16/458 , C23C16/46 , C23C16/455
Abstract: The present disclosure generally relates to a process chamber for processing of semiconductor substrates. The process chamber includes an upper lamp assembly, a lower lamp assembly, a substrate support, an upper window disposed between the substrate support and the upper lamp assembly, a lower window disposed between the lower lamp assembly and the substrate support, an inject ring, and a base ring. Each of the upper lamp assembly and the lower lamp assembly include vertically oriented lamp apertures for the placement of heating lamps therein. The inject ring includes gas injectors disposed therethrough and the base ring includes a substrate transfer passage, a lower chamber exhaust passage, and one or more upper chamber exhaust passages. The gas injectors are disposed over the substrate transfer passage and across from the lower chamber exhaust passage and the one or more upper chamber exhaust passages.
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公开(公告)号:US20170330960A1
公开(公告)日:2017-11-16
申请号:US15242078
申请日:2016-08-19
Applicant: Applied Materials, Inc.
Inventor: Matthias BAUER , Hans-Joachim Ludwig GOSSMANN , Benjamin COLOMBEAU
IPC: H01L29/66 , H01L21/02 , H01L29/26 , H01L29/78 , H01L29/08 , H01L29/06 , H01L21/306 , H01L29/167 , H01L29/16 , H01L29/20
CPC classification number: H01L29/66795 , H01L21/02439 , H01L21/02447 , H01L21/02532 , H01L21/02576 , H01L21/0262 , H01L21/02645 , H01L21/02658 , H01L21/30604 , H01L29/0673 , H01L29/0847 , H01L29/1608 , H01L29/165 , H01L29/167 , H01L29/20 , H01L29/26 , H01L29/6656 , H01L29/66636 , H01L29/7848 , H01L29/7851
Abstract: A finFET device includes an n-doped source and/or drain extension that is disposed between a gate spacer of the finFET and a bulk semiconductor portion of the semiconductor substrate on which the n-doped source or drain extension is disposed. The n-doped source or drain extension is formed by a selective epitaxial growth (SEG) process in a cavity formed proximate the gate spacer.
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公开(公告)号:US20190051531A1
公开(公告)日:2019-02-14
申请号:US16159608
申请日:2018-10-12
Applicant: Applied Materials, Inc.
Inventor: Matthias BAUER
IPC: H01L21/285 , H01L21/8238 , H01L21/02
Abstract: Methods for selective silicide formation are described herein. The methods are generally utilized in conjunction with contact structure integration schemes and provide for improved silicide formation characteristics. In one implementation, a silicide material is selectively formed on source/drain (S/D) regions at a temperature less than about 550° C. The resulting silicide is believed to exhibit desirable contact resistance and applicability in advanced contact integration schemes.
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公开(公告)号:US20180240893A9
公开(公告)日:2018-08-23
申请号:US15792449
申请日:2017-10-24
Applicant: Applied Materials, Inc.
Inventor: Matthias BAUER , Hans-Joachim L. GOSSMANN , Benjamin COLOMBEAU
IPC: H01L29/66 , H01L21/02 , H01L29/26 , H01L29/78 , H01L29/08 , H01L29/06 , H01L21/306 , H01L29/167 , H01L29/16 , H01L29/20
CPC classification number: H01L29/26 , H01L21/02447 , H01L21/02532 , H01L21/02576 , H01L21/0262 , H01L21/02645 , H01L21/02658 , H01L21/30604 , H01L29/0673 , H01L29/0847 , H01L29/1608 , H01L29/165 , H01L29/167 , H01L29/20 , H01L29/66636 , H01L29/66795 , H01L29/7848 , H01L29/7851
Abstract: A finFET device includes an n-doped source and/or drain extension that is disposed between a gate spacer of the finFET and a bulk semiconductor portion of the semiconductor substrate on which the n-doped source or drain extension is disposed. The n-doped source or drain extension is formed by a selective epitaxial growth (SEG) process in a cavity formed proximate the gate spacer.
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公开(公告)号:US20180166288A1
公开(公告)日:2018-06-14
申请号:US15832571
申请日:2017-12-05
Applicant: Applied Materials, Inc.
Inventor: Hua CHUNG , Matthias BAUER , Schubert S. CHU , Satheesh KUPPURAO
IPC: H01L21/285 , H01L29/167 , H01L29/45
CPC classification number: H01L21/28518 , H01L21/02043 , H01L21/02532 , H01L21/285 , H01L21/32053 , H01L21/324 , H01L29/0847 , H01L29/165 , H01L29/167 , H01L29/456 , H01L29/665 , H01L29/7833 , H01L29/7848
Abstract: The present disclosure generally relates to methods of selectively forming titanium silicides on substrates. The methods are generally utilized in conjunction with contact structure integration schemes. In one embodiment, a titanium silicide material is selectively formed on a substrate as an interfacial layer on a source/drain region. The titanium silicide layer may be formed at a temperature within range of about 400 degrees Celsius to about 500 degrees Celsius.
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公开(公告)号:US20220367216A1
公开(公告)日:2022-11-17
申请号:US17317684
申请日:2021-05-11
Applicant: Applied Materials, Inc.
Inventor: Tetsuya ISHIKAWA , Swaminathan T. SRINIVASAN , Matthias BAUER , Ala MORADIAN , Manjunath SUBBANNA , Kartik Bhupendra SHAH , Kostiantyn ACHKASOV , Errol Antonio C. SANCHEZ , Michael R. RICE , Marc SHULL , Ji-Dih HU
Abstract: The present disclosure generally relates to an epitaxial chamber for processing of semiconductor substrates. In one example, the epitaxial chamber has a chamber body assembly. The chamber body assembly includes a lower window and an upper window, wherein chamber body assembly, the lower window and the upper window enclose an internal volume. A susceptor assembly is disposed in the internal volume. The epitaxial chamber also has a plurality of temperature control elements. The plurality of temperature control elements include one or more of an upper lamp module, a lower lamp module, an upper heater, a lower heater, or a heated gas passage.
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公开(公告)号:US20220364231A1
公开(公告)日:2022-11-17
申请号:US17317342
申请日:2021-05-11
Applicant: Applied Materials, Inc.
Inventor: Tetsuya ISHIKAWA , Swaminathan T. SRINIVASAN , Matthias BAUER , Ala MORADIAN , Manjunath SUBBANNA , Kartik Bhupendra SHAH , Errol Antonio C. SANCHEZ , Sohrab ZOKAEI , Michael R. RICE , Peter REIMER
IPC: C23C16/455 , B01J4/00 , C23C16/44
Abstract: The present disclosure generally relates to gas inject apparatus for a process chamber for processing of semiconductor substrates. The gas inject apparatus include one or more gas injectors which are configured to be coupled to the process chamber. Each of the gas injectors are configured to receive a process gas and distribute the process gas across one or more gas outlets. The gas injectors include a plurality of pathways, a fin array, and a baffle array. The gas injectors are individually heated. A gas mixture assembly is also utilized to control the concentration of process gases flown into a process volume from each of the gas injectors. The gas mixture assembly enables the concentration as well as the flow rate of the process gases to be controlled.
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公开(公告)号:US20200241580A1
公开(公告)日:2020-07-30
申请号:US16848594
申请日:2020-04-14
Applicant: Applied Materials, Inc.
Inventor: Matthias BAUER
Abstract: Implementations of the present disclosure generally relate to one or more flow ratio controllers and one or more gas injection inserts in the semiconductor processing chamber. In one implementation, an apparatus includes a first flow ratio controller including a first plurality of flow controllers, a second flow ratio controller including a second plurality of flow controllers, and a gas injection insert including a first portion and a second portion. The first portion includes a first plurality of channels and the second portion includes a second plurality of channels. The apparatus further includes a plurality of gas lines connecting the first and second pluralities of flow controllers to the first and second pluralities of channels. One or more gas lines of the plurality of gas lines are each connected to a channel of the first plurality of channels and a channel of the second plurality of channels.
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