公开(公告)号：US20220406790A1

公开(公告)日：2022-12-22

申请号：US17861412

申请日：2022-07-11

Applicant: Applied Materials, Inc.

Inventor： Tom Ho Wing Yu ,  Nobuyuki Sasaki ,  Jianxin Lei ,  Wenting Hou ,  Rongjun Wang ,  Tza-Jing Gung

IPC: H01L27/108

Abstract: Bit line stacks and methods of forming bit line stacks are described herein. A bit line stack comprises: a polysilicon layer; an adhesion layer on the polysilicon layer; a barrier metal layer on the adhesion layer; an interface layer on the barrier metal layer; a resistance reducing layer on the interface layer; and a conductive layer on the resistance reducing layer. A bit line stack having the resistance reducing layer has a resistance at least 5% lower than a comparable bit line stack without the resistance reducing layer. The resistance reducing layer may include silicon oxide or silicon nitride. The resistance reducing layer may be formed using one or more of a physical vapor deposition (PVD), a radio frequency-PVD, a pulsed-PVD, chemical vapor deposition (CVD), atomic layer deposition (ALD) or sputtering process.

公开(公告)号：US20210327717A1

公开(公告)日：2021-10-21

申请号：US16849988

申请日：2020-04-15

Applicant: Applied Materials, Inc.

Inventor： Tom Ho Wing Yu ,  Nobuyuki Sasaki ,  Kazuya Daito

IPC: H01L21/285 ,  H01L21/02 ,  H01L21/67 ,  H01L21/687

Abstract: Methods and apparatus for the formation of cobalt disilicide are described. Some embodiments of the disclosure provide in-situ methods of forming cobalt disilicide. The resulting films are smoother and have lower resistance and resistivity than films formed by similar ex-situ methods. Some embodiments of the disclosure provide apparatus for performing the described methods without an air break between processes.

公开(公告)号：US12094773B2

公开(公告)日：2024-09-17

申请号：US17857341

申请日：2022-07-05

Applicant: Applied Materials, Inc.

Inventor： Xi Cen ,  Kai Wu ,  Min Heon ,  Wei Min Chan ,  Tom Ho Wing Yu ,  Peiqi Wang ,  Ju Ik Kang ,  Feihu Wang ,  Nobuyuki Sasaki ,  Chunming Zhou

IPC: H01L21/768 ,  C23C16/04 ,  H01L21/02

CPC classification number: H01L21/76879 ,  C23C16/045 ,  H01L21/0262

Abstract: Method for forming tungsten gap fill on a structure, including high aspect ratio structures includes depositing a tungsten liner in the structure using a physical vapor deposition (PVD) process with high ionization and an ambient gas of argon or krypton. The PVD process is performed at a temperature of approximately 20 degrees Celsius to approximately 300 degrees Celsius. The method further includes treating the structure with a nitridation process and depositing bulk fill tungsten into the structure using a chemical vapor deposition (CVD) process to form a seam suppressed boron free tungsten fill. The CVD process is performed at a temperature of approximately 300 degrees Celsius to approximately 500 degrees Celsius and at a pressure of approximately 5 Torr to approximately 300 Torr.

公开(公告)号：US11626410B2

公开(公告)日：2023-04-11

申请号：US17861412

申请日：2022-07-11

Applicant: Applied Materials, Inc.

Inventor： Tom Ho Wing Yu ,  Nobuyuki Sasaki ,  Jianxin Lei ,  Wenting Hou ,  Rongjun Wang ,  Tza-Jing Gung

IPC: H01L27/108

Abstract: Bit line stacks and methods of forming bit line stacks are described herein. A bit line stack comprises: a polysilicon layer; an adhesion layer on the polysilicon layer; a barrier metal layer on the adhesion layer; an interface layer on the barrier metal layer; a resistance reducing layer on the interface layer; and a conductive layer on the resistance reducing layer. A bit line stack having the resistance reducing layer has a resistance at least 5% lower than a comparable bit line stack without the resistance reducing layer. The resistance reducing layer may include silicon oxide or silicon nitride. The resistance reducing layer may be formed using one or more of a physical vapor deposition (PVD), a radio frequency-PVD, a pulsed-PVD, chemical vapor deposition (CVD), atomic layer deposition (ALD) or sputtering process.

公开(公告)号：US11798845B2

公开(公告)日：2023-10-24

申请号：US17082602

申请日：2020-10-28

Applicant: Applied Materials, Inc.

Inventor： Xi Cen ,  Kai Wu ,  Min Heon ,  Wei Min Chan ,  Tom Ho Wing Yu ,  Peiqi Wang ,  Ju Ik Kang ,  Feihu Wang ,  Nobuyuki Sasaki ,  Chunming Zhou

IPC: H01L21/768 ,  H01L21/02 ,  C23C16/04

CPC classification number: H01L21/76879 ,  C23C16/045 ,  H01L21/0262

Abstract: Method for forming tungsten gap fill on a structure, including high aspect ratio structures includes depositing a tungsten liner in the structure using a physical vapor deposition (PVD) process with high ionization and an ambient gas of argon or krypton. The PVD process is performed at a temperature of approximately 20 degrees Celsius to approximately 300 degrees Celsius. The method further includes treating the structure with a nitridation process and depositing bulk fill tungsten into the structure using a chemical vapor deposition (CVD) process to form a seam suppressed boron free tungsten fill. The CVD process is performed at a temperature of approximately 300 degrees Celsius to approximately 500 degrees Celsius and at a pressure of approximately 5 Torr to approximately 300 Torr.

公开(公告)号：US11637107B2

公开(公告)日：2023-04-25

申请号：US17351223

申请日：2021-06-17

Applicant: Applied Materials, Inc.

Inventor： Tom Ho Wing Yu ,  Nobuyuki Sasaki ,  Jianxin Lei ,  Wenting Hou ,  Rongjun Wang ,  Tza-Jing Gung

IPC: H01L27/108

Abstract: Bit line stacks and methods of forming bit line stacks are described herein. A bit line stack comprises: a polysilicon layer; an adhesion layer on the polysilicon layer; a barrier metal layer on the adhesion layer; an interface layer on the barrier metal layer; a resistance reducing layer on the interface layer; and a conductive layer on the resistance reducing layer. A bit line stack having the resistance reducing layer has a resistance at least 5% lower than a comparable bit line stack without the resistance reducing layer. The resistance reducing layer may include silicon oxide or silicon nitride. The resistance reducing layer may be formed using one or more of a physical vapor deposition (PVD), a radio frequency-PVD, a pulsed-PVD, chemical vapor deposition (CVD), atomic layer deposition (ALD) or sputtering process.

公开(公告)号：US20220406788A1

公开(公告)日：2022-12-22

申请号：US17351223

申请日：2021-06-17

Applicant: Applied Materials, Inc.

Inventor： Tom Ho Wing Yu ,  Nobuyuki Sasaki ,  Jianxin Lei ,  Wenting Hou ,  Rongjun Wang ,  Tza-Jing Gung

IPC: H01L27/108

Abstract: Bit line stacks and methods of forming bit line stacks are described herein. A bit line stack comprises: a polysilicon layer; an adhesion layer on the polysilicon layer; a barrier metal layer on the adhesion layer; an interface layer on the barrier metal layer; a resistance reducing layer on the interface layer; and a conductive layer on the resistance reducing layer. A bit line stack having the resistance reducing layer has a resistance at least 5% lower than a comparable bit line stack without the resistance reducing layer. The resistance reducing layer may include silicon oxide or silicon nitride. The resistance reducing layer may be formed using one or more of a physical vapor deposition (PVD), a radio frequency-PVD, a pulsed-PVD, chemical vapor deposition (CVD), atomic layer deposition (ALD) or sputtering process.