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    DEVICES AND METHODS FOR DRAM LEAKAGE REDUCTION
    2.
    发明公开
    DEVICES AND METHODS FOR DRAM LEAKAGE REDUCTION 审中-公开

    公开(公告)号：US20240049443A1

    公开(公告)日：2024-02-08

    申请号：US17881969

    申请日：2022-08-05

    Applicant: Applied Materials, Inc.

    Inventor： Armin Saeedi Vahdat ,  John Hautala ,  Yan Zhang ,  Johannes M. van Meer

    IPC: H01L27/108

    CPC classification number: H01L27/10876 ,  H01L27/10823

    Abstract: Approaches for reducing GIDL are disclosed. In one example, a method of forming a DRAM device may include forming a trench in a substrate layer, providing a first gate oxide layer along a sidewall and a bottom surface of the trench, and forming a first gate material within the trench. The method may further include removing the first gate oxide layer along an upper portion of the sidewall of the trench by delivering ions into the upper portion of the trench at a non-zero angle relative to a perpendicular extending from an upper surface of the substrate layer, and forming a second gate oxide layer along the upper portion of the sidewall of the trench, wherein a first dielectric constant of the first gate oxide layer is greater than a second dielectric constant of the second gate oxide layer.

    BOTTOM IMPLANT AND AIRGAP ISOLATION FOR NANOSHEET SEMICONDUCTOR DEVICES
    4.
    发明申请
    BOTTOM IMPLANT AND AIRGAP ISOLATION FOR NANOSHEET SEMICONDUCTOR DEVICES 有权

    公开(公告)号：US20230089482A1

    公开(公告)日：2023-03-23

    申请号：US17480482

    申请日：2021-09-21

    Applicant: Applied Materials, Inc.

    Inventor： Yan Zhang ,  Johannes M. van Meer ,  Naushad K. Variam

    IPC: H01L21/764 ,  H01L27/092 ,  H01L21/8238

    Abstract: A semiconductor manufacturing process and semiconductor device having an airgap to isolate bottom implant portions of a substrate from upper source and drain device structure to reduce bottom current leakage and parasitic capacitance with an improved scalability on n-to-p spacing scaling. The disclosed device can be implanted to fabricate nanosheet FET and other such semiconductor device. The airgap is formed by etching into the substrate, below a trench in a vertical and horizontal direction. The trench is then filled with dielectric and upper device structure formed on either side of the dielectric filler trench.

    Ion implantation process to form punch through stopper
    5.
    发明授权
    Ion implantation process to form punch through stopper 有权

    公开(公告)号：US12300494B2

    公开(公告)日：2025-05-13

    申请号：US17548002

    申请日：2021-12-10

    Applicant: Applied Materials, Inc.

    Inventor： Yan Zhang ,  Johannes M. van Meer ,  Naushad K. Variam

    IPC: H01L21/265 ,  H10D64/01

    Abstract: Approaches herein provide devices and methods for forming optimized gate-all-around transistors. One method may include forming a well by directing a first ion species into a substrate of a device, forming a plurality of alternating first and second layers over the well, and forming a dummy gate and a spacer over the plurality of alternating first and second layers. The method may further include removing a portion of the plurality of alternating first and second layers to expose an upper surface of the well, forming a punch through stopper in the well by directing a second ion species into the exposed upper surface of the well, etching the plurality of nanosheets to laterally recess the second layers relative to the first layers, and forming an inner spacer along the first and second layers.

    HIGH ASPECT RATIO TAPER IMPROVEMENT USING DIRECTIONAL DEPOSITION
    7.
    发明公开
    HIGH ASPECT RATIO TAPER IMPROVEMENT USING DIRECTIONAL DEPOSITION 审中-公开

    公开(公告)号：US20230257872A1

    公开(公告)日：2023-08-17

    申请号：US17673667

    申请日：2022-02-16

    Applicant: Applied Materials, Inc.

    Inventor： Armin Saeedi Vahdat ,  Yan Zhang ,  John Hautala

    IPC: C23C16/30 ,  C23C16/40 ,  H01L21/306 ,  C23C28/04

    CPC classification number: C23C16/303 ,  C23C16/40 ,  H01L21/30621 ,  C23C28/04

    Abstract: Disclosed are approaches for forming semiconductor device cavities. One method may include providing a set of semiconductor structures defining an opening, wherein the opening has a first opening width along an upper portion of the opening and a second opening width along a lower portion of the opening, the first opening width being greater than the second opening width. The method may further include forming a blocking layer along the set of semiconductor structures by delivering a material at a non-zero angle of inclination relative to a normal extending perpendicular from a top surface of the set of semiconductor structures. The blocking layer may be formed along the upper portion of the opening without being formed along the lower portion of the opening, and wherein an opening through the blocking layer is present above the opening.

    ION IMPLANTATION PROCESS TO FORM PUNCH THROUGH STOPPER
    10.
    发明公开
    ION IMPLANTATION PROCESS TO FORM PUNCH THROUGH STOPPER 审中-公开

    公开(公告)号：US20230187210A1

    公开(公告)日：2023-06-15

    申请号：US17548002

    申请日：2021-12-10

    Applicant: Applied Materials, Inc.

    Inventor： Yan Zhang ,  Johannes M. van Meer ,  Naushad K. Variam

    IPC: H01L21/265 ,  H01L29/66

    CPC classification number: H01L21/265 ,  H01L29/66545 ,  H01L29/66553

    Abstract: Approaches herein provide devices and methods for forming optimized gate-all-around transistors. One method may include forming a well by directing a first ion species into a substrate of a device, forming a plurality of alternating first and second layers over the well, and forming a dummy gate and a spacer over the plurality of alternating first and second layers. The method may further include removing a portion of the plurality of alternating first and second layers to expose an upper surface of the well, forming a punch through stopper in the well by directing a second ion species into the exposed upper surface of the well, etching the plurality of nanosheets to laterally recess the second layers relative to the first layers, and forming an inner spacer along the first and second layers.

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