公开(公告)号：US12142534B2

公开(公告)日：2024-11-12

申请号：US17194825

申请日：2021-03-08

Applicant: Applied Materials, Inc.

Inventor： Sankuei Lin ,  Ajay Bhatnagar ,  Nitin Ingle

IPC: H01L27/092 ,  H01L21/02 ,  H01L21/768 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786

Abstract: Processing methods may be performed to expose a contact region on a semiconductor substrate. The methods may include selectively removing a first region of a silicon material between source/drain regions of a semiconductor substrate to expose a first region of oxide material. The methods may include forming a liner over the first region of oxide material and contacting second regions of the silicon material proximate the source/drain regions of the semiconductor substrate. The methods may also include selectively removing the second regions of the silicon material proximate the source/drain regions of the semiconductor substrate to expose a second region of the oxide material. The methods may further include selectively removing the second region of the oxide material from a surface of a contact in the semiconductor structure.

公开(公告)号：US11735467B2

公开(公告)日：2023-08-22

申请号：US17558848

申请日：2021-12-22

Applicant: Applied Materials, Inc.

Inventor： Ashish Pal ,  Gaurav Thareja ,  Sankuei Lin ,  Ching-Mei Hsu ,  Nitin K. Ingle ,  Ajay Bhatnagar ,  Anchuan Wang

IPC: H01L21/764 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L27/092 ,  H01L29/417

CPC classification number: H01L21/764 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823864 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/41791

Abstract: Processing methods may be performed to form an airgap spacer on a semiconductor substrate. The methods may include forming a spacer structure including a first material and a second material different from the first material. The methods may include forming a source/drain structure. The source/drain structure may be offset from the second material of the spacer structure by at least one other material. The methods may also include etching the second material from the spacer structure to form the airgap. The source/drain structure may be unexposed to etchant materials during the etching.

公开(公告)号：US20230369453A1

公开(公告)日：2023-11-16

申请号：US17744238

申请日：2022-05-13

Applicant: Applied Materials, Inc.

Inventor： Yan Zhang ,  Johannes M. van Meer ,  Sankuei Lin ,  Baonian Guo ,  Naushad K. Variam

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L29/40

CPC classification number: H01L29/66545 ,  H01L29/66553 ,  H01L29/42392 ,  H01L29/0665 ,  H01L29/78696 ,  H01L29/401

Abstract: A method for forming a nanosheet device. The method may include providing a heterostructure device stack above a semiconductor substrate. The method may include patterning the heterostructure device stack to define a dummy gate region, and before forming a source drain recess adjacent the dummy gate region, selectively removing a first set of sacrificial layers of the heterostructure device stack within the dummy gate region.

公开(公告)号：US09685374B1

公开(公告)日：2017-06-20

申请号：US15096997

申请日：2016-04-12

Applicant: Applied Materials, Inc.

Inventor： Sankuei Lin ,  Ajay Bhatnagar

IPC: H01L21/00 ,  H01L23/00 ,  H01L27/00 ,  H01L29/00 ,  H01L21/768 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/08 ,  H01L29/06 ,  H01L29/161 ,  H01L29/16 ,  H01L29/165 ,  H01L29/24 ,  H01L29/267 ,  H01L29/78 ,  H01L23/535

CPC classification number: H01L21/76897 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823871 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/24 ,  H01L29/267 ,  H01L29/7848 ,  H01L29/785 ,  H01L2029/7858

Abstract: Embodiments described herein generally relate to forming a semiconductor structure. In one embodiment, a method of forming a semiconductor structure is formed herein. The method includes exposing an oxide layer of the semiconductor structure, depositing a polysilicon layer on the semiconductor structure, filling a first gap formed by exposing the oxide layer, depositing a hard mask on the polysilicon layer, selectively removing the hard mask and the polysilicon layer, depositing an oxide layer on the semiconductor structure, filling a second gap formed by selectively removing the hard mask and polysilicon layer, exposing the polysilicon layer deposited on the semiconductor structure, selectively removing the polysilicon layer from the first gap, and selectively removing an etch stop layer from a surface of a contact in the semiconductor structure.

公开(公告)号：US11211286B2

公开(公告)日：2021-12-28

申请号：US16277104

申请日：2019-02-15

Applicant: Applied Materials, Inc.

Inventor： Ashish Pal ,  Gaurav Thareja ,  Sankuei Lin ,  Ching-Mei Hsu ,  Nitin K. Ingle ,  Ajay Bhatnagar ,  Anchuan Wang

IPC: H01L21/764 ,  H01L29/06 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/78 ,  H01L27/092 ,  H01L29/417

Abstract: Processing methods may be performed to form an airgap spacer on a semiconductor substrate. The methods may include forming a spacer structure including a first material and a second material different from the first material. The methods may include forming a source/drain structure. The source/drain structure may be offset from the second material of the spacer structure by at least one other material. The methods may also include etching the second material from the spacer structure to form the airgap. The source/drain structure may be unexposed to etchant materials during the etching.

公开(公告)号：US10943834B2

公开(公告)日：2021-03-09

申请号：US15918613

申请日：2018-03-12

Applicant: Applied Materials, Inc.

Inventor： Sankuei Lin ,  Ajay Bhatnagar ,  Nitin Ingle

IPC: H01L21/82 ,  H01L21/76 ,  H01L21/02 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/417 ,  H01L29/786 ,  H01L21/768 ,  H01L29/08

Abstract: Processing methods may be performed to expose a contact region on a semiconductor substrate. The methods may include selectively removing a first region of a silicon material between source/drain regions of a semiconductor substrate to expose a first region of oxide material. The methods may include forming a liner over the first region of oxide material and contacting second regions of the silicon material proximate the source/drain regions of the semiconductor substrate. The methods may also include selectively removing the second regions of the silicon material proximate the source/drain regions of the semiconductor substrate to expose a second region of the oxide material. The methods may further include selectively removing the second region of the oxide material from a surface of a contact in the semiconductor structure.

公开(公告)号：US12230691B2

公开(公告)日：2025-02-18

申请号：US17744238

申请日：2022-05-13

Applicant: Applied Materials, Inc.

Inventor： Yan Zhang ,  Johannes M. van Meer ,  Sankuei Lin ,  Baonian Guo ,  Naushad K. Variam

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423 ,  H01L29/786

Abstract: A method for forming a nanosheet device. The method may include providing a heterostructure device stack above a semiconductor substrate. The method may include patterning the heterostructure device stack to define a dummy gate region, and before forming a source drain recess adjacent the dummy gate region, selectively removing a first set of sacrificial layers of the heterostructure device stack within the dummy gate region.

公开(公告)号：US20240055269A1

公开(公告)日：2024-02-15

申请号：US17886285

申请日：2022-08-11

Applicant: Applied Materials, Inc.

Inventor： Sankuei Lin ,  Changwoo Sun ,  Pradeep K. Subrahmanyan

IPC: H01L21/311 ,  H01L27/115

CPC classification number: H01L21/31116 ,  H01L27/115 ,  H01L21/31144

Abstract: A three-dimensional (3D) NAND memory structure may include alternating layers of materials arranged in a vertical stack on a silicon substrate, such as alternating oxide and nitride layers. The alternating nitride layers may later be removed, and the recesses may be filled with a conductive material to form word lines for the memory array. To avoid pinching off these recesses with silicon byproducts from a traditional wet etch, a dry etch may be instead be used to remove the nitrite layers. To protect the silicon substrate, a first insulating layer may be deposited at the bottom of the slit to cover the exposed silicon substrate before performing the dry etch. After applying a second insulating layer to cover the alternating oxide/nitride layers, a directional etch may punch through both insulating layers to again expose the silicon substrate before applying a solid material fill in the slit.

公开(公告)号：US20220115263A1

公开(公告)日：2022-04-14

申请号：US17558848

申请日：2021-12-22

Applicant: Applied Materials, Inc.

Inventor： Ashish Pal ,  Gaurav Thareja ,  Sankuei Lin ,  Ching-Mei Hsu ,  Nitin K. Ingle ,  Ajay Bhatnagar ,  Anchuan Wang

IPC: H01L21/764 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L27/092

Abstract: Processing methods may be performed to form an airgap spacer on a semiconductor substrate. The methods may include forming a spacer structure including a first material and a second material different from the first material. The methods may include forming a source/drain structure. The source/drain structure may be offset from the second material of the spacer structure by at least one other material. The methods may also include etching the second material from the spacer structure to form the airgap. The source/drain structure may be unexposed to etchant materials during the etching.

公开(公告)号：US20210217668A1

公开(公告)日：2021-07-15

申请号：US17194825

申请日：2021-03-08

Applicant: Applied Materials, Inc.

Inventor： Sankuei Lin ,  Ajay Bhatnagar ,  Nitin Ingle

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/417 ,  H01L29/786 ,  H01L21/768 ,  H01L21/02 ,  H01L29/08

Abstract: Processing methods may be performed to expose a contact region on a semiconductor substrate. The methods may include selectively removing a first region of a silicon material between source/drain regions of a semiconductor substrate to expose a first region of oxide material. The methods may include forming a liner over the first region of oxide material and contacting second regions of the silicon material proximate the source/drain regions of the semiconductor substrate. The methods may also include selectively removing the second regions of the silicon material proximate the source/drain regions of the semiconductor substrate to expose a second region of the oxide material. The methods may further include selectively removing the second region of the oxide material from a surface of a contact in the semiconductor structure.