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公开(公告)号：US11822797B1
公开(公告)日：2023-11-21
申请号：US18304247
申请日：2023-04-20
Inventor： Jin Dai , Yunsen Zhang
CPC classification number: G06F3/0629 , G06F3/0607 , G06F3/0685
Abstract: An object computational storage system, a data processing method, a client end and a storage medium are disclosed, belonging to the field of electrical digital data processing, including a storage control device and a storage chip or a storage disk connected thereto. The storage control device is a computational storage management system, and performs the following processing: receiving an external data processing request, parsing information of a specified storage object, information of a specified function, and information of input data carried by the data processing request; when it is determined that calling the specified function for the specified storage object is supported, calling the specified function to perform computation on data of the specified storage object according to the input data; and returning a computation result to a sender of the data processing request.
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Patent Agency Ranking
公开(公告)号：US20250048615A1
公开(公告)日：2025-02-06
申请号：US18692912
申请日：2023-06-08
Inventor： Xuezheng Ai , Xiangsheng Wang , Guilei Wang , Jin Dai , Chao Zhao , Wenhua Gui
IPC: H10B12/00
Abstract: A 3D stacked semiconductor device, a manufacturing method therefor, and an electronic equipment are disclosed. The 3D stacked semiconductor device includes a plurality of transistors distributed in different layers and stacked along a direction perpendicular to a base substrate; a word line penetrating through the transistors of the different layers; and a plurality of protective layers corresponding to the plurality of transistors respectively; wherein each transistor includes a semiconductor layer surrounding a side wall of the word line, a gate insulation layer disposed between the side wall of the word line and the semiconductor layer, a plurality of semiconductor layers of the plurality of transistors are disposed at intervals in a direction in which the word line extends; each of the protective layers respectively surrounds and covers an outer side wall of a corresponding semiconductor layer, and two adjacent protective layers are disconnected from each other.
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公开(公告)号：US11825642B1
公开(公告)日：2023-11-21
申请号：US18312389
申请日：2023-05-04
Inventor： Jin Dai , Yong Yu , Jing Liang
IPC: H10B12/00
CPC classification number: H10B12/00
Abstract: A memory cell, a 3D memory and a preparation thereof, and an electronic device. The memory cell includes a first transistor and a second transistor disposed on a substrate, the first transistor includes a first gate, a first electrode, a second electrode and a first semiconductor layer disposed on the substrate; the second transistor includes a third electrode, a fourth electrode, a second gate extending in a direction perpendicular to the substrate and a second semiconductor layer surrounding a sidewall of the second gate which are disposed on the substrate, the second semiconductor layer includes a second source contact region and a second drain contact region arranged at intervals, a channel between the second source contact region and the second drain contact region is a horizontal channel.
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公开(公告)号：US12238918B1
公开(公告)日：2025-02-25
申请号：US18754418
申请日：2024-06-26
Inventor： Wenhua Gui , Xuezheng Ai , Guilei Wang , Jin Dai , Xiangsheng Wang
IPC: H10B12/00
Abstract: Provided are a semiconductor device and manufacturing method thereof, and an electronic device. The semiconductor device includes multiple storage cells distributed in a direction perpendicular to a base substrate, the multiple storage cells include multiple transistors and capacitors distributed in different layers and stacked in the direction perpendicular to the base substrate; a word line penetrating different layers and extending in the direction perpendicular to the base substrate; a transistor includes a first source/drain electrode, a second source/drain electrode and a semiconductor layer surrounding a sidewall of the word line; first insulating layers and conductive layers alternately distributed in the direction perpendicular to the base substrate, at least one first hole penetrating the different layers; and the second electrode of the capacitor includes an inner electrode disposed in the first hole on the first electrode.
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公开(公告)号：US12235766B2
公开(公告)日：2025-02-25
申请号：US18609230
申请日：2024-03-19
Inventor： Jin Dai
IPC: G06F12/0817 , G06F3/06
Abstract: A CXL memory module, a memory data swap method and a computer system. The CXL memory module may include a flash memory chip, a memory chip, and a controller chip connected with the flash memory chip and the memory chip. The controller chip is configured to be able to swap a part of data in the memory chip into the flash memory chip.
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公开(公告)号：US11928345B1
公开(公告)日：2024-03-12
申请号：US18312968
申请日：2023-05-05
Inventor： Jin Dai , Yunsen Zhang
IPC: G06F3/06
CPC classification number: G06F3/0631 , G06F3/0604 , G06F3/0679
Abstract: Provided are a computational storage system, computational storage processor, solid-state drive (SSD) and data storing method. The method may include receiving a first storing instruction based on a storage object, generating a second storing instruction based on a flash memory address according to information carried by the first storing instruction and SSD resource information maintained locally, and sending the generated second storing instruction to the SSD. The SSD resource information may include resource occupation information in the SSD. Generating the second storing instruction may include parsing an identification of a storage object, data length information and a starting source address of entire data, allocating a flash memory address or addresses in one or more SSDs for storing data of the storage object according to the data length information and the resource occupancy information in the SSD, and generating the second storing instructions for each SSD.
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