-
公开(公告)号：US11825642B1
公开(公告)日：2023-11-21
申请号：US18312389
申请日：2023-05-04
Inventor： Jin Dai , Yong Yu , Jing Liang
IPC: H10B12/00
CPC classification number: H10B12/00
Abstract: A memory cell, a 3D memory and a preparation thereof, and an electronic device. The memory cell includes a first transistor and a second transistor disposed on a substrate, the first transistor includes a first gate, a first electrode, a second electrode and a first semiconductor layer disposed on the substrate; the second transistor includes a third electrode, a fourth electrode, a second gate extending in a direction perpendicular to the substrate and a second semiconductor layer surrounding a sidewall of the second gate which are disposed on the substrate, the second semiconductor layer includes a second source contact region and a second drain contact region arranged at intervals, a channel between the second source contact region and the second drain contact region is a horizontal channel.
-
公开(公告)号：US20230171940A1
公开(公告)日：2023-06-01
申请号：US17817671
申请日：2022-08-05
Inventor： Deyuan XIAO , Yong Yu , Guangsu Shao
IPC: H01L27/108
CPC classification number: H01L27/10873 , H01L27/10814 , H01L27/10885
Abstract: The present disclosure provides a manufacturing method of a semiconductor structure and a semiconductor structure. The manufacturing method of a semiconductor structure includes: providing a substrate; forming a plurality of silicon pillars arranged in an array on the substrate; pre-processing the silicon pillar, to form an active pillar, where along a first direction, the active pillar includes a first segment, a second segment, and a third segment that are connected sequentially; forming a gate oxide layer on sidewalls of each of the second segment and the third segment; and forming a gate dielectric layer on the gate oxide layer, where along the first direction, the gate dielectric layer is shorter than the gate oxide layer, and a top surface of the gate dielectric layer is flush with that of the third segment.
-
公开(公告)号：US20230363140A1
公开(公告)日：2023-11-09
申请号：US17933531
申请日：2022-09-20
Inventor： Guangsu SHAO , Deyuan Xiao , Yong Yu
IPC: H01L27/108 , H01L29/24
CPC classification number: H01L27/10805 , H01L27/10885 , H01L27/10891 , H01L29/247
Abstract: The present disclosure relates to the technical field of semiconductors, and provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a base, and bit lines, word lines, active pillars, and a memory structure that are located on the base. The bit line extends along a first direction, the word line extends along a second direction, the first direction is one of a direction perpendicular to a surface of the base or a direction parallel to the surface of the base, and the second direction is the other of the direction perpendicular to the surface of the base or the direction parallel to the surface of the base. The active pillars are parallel to the base and arranged at intervals, the word line surrounds a channel region of the active pillar, the memory structure surrounds a support region of the active pillar.
-
Patent Agency Ranking
公开(公告)号：US20230171941A1
公开(公告)日：2023-06-01
申请号：US17817750
申请日：2022-08-05
Inventor： Deyuan XIAO , Yong Yu , Guangsu Shao
IPC: H01L27/108
CPC classification number: H01L27/10873 , H01L27/10814 , H01L27/10885
Abstract: The present disclosure provides a manufacturing method of a semiconductor structure and a semiconductor structure, and relates to the technical field of semiconductors. The manufacturing method of a semiconductor structure includes: providing a substrate; forming active pillars arranged at intervals on the substrate, the active pillar includes a first segment, a second segment, and a third segment that are connected sequentially along a first direction; forming a gate oxide layer on sidewalls of each of the second segment and the third segment; and forming a word line structure on a sidewall of the gate oxide layer, the word line structure includes a first word line structure and a second word line structure that are made of different materials, and the first word line structure is connected to the sidewall of the gate oxide layer, and partially covers the second word line structure.
-
公开(公告)号：US20230171938A1
公开(公告)日：2023-06-01
申请号：US17817405
申请日：2022-08-04
Inventor： Deyuan XIAO , Yong Yu , Guangsu Shao
IPC: H01L27/108 , H01L29/78
CPC classification number: H01L27/10864 , H01L27/10891 , H01L27/10885 , H01L29/7827
Abstract: The present disclosure provides a manufacturing method of a semiconductor structure and a semiconductor structure. The manufacturing method of a semiconductor structure includes: providing a substrate; forming a plurality of active pillars arranged in an array on the substrate, where the active pillar includes a first segment, a second segment, and a third segment that are connected sequentially, and along a second direction, a cross-sectional area of the second segment is smaller than those of the first segment and the third segment; forming a gate oxide layer on a sidewall of the second segment, a top surface of the first segment, and a bottom surface of the third segment; and forming a gate dielectric layer on the gate oxide layer, where the gate dielectric layer is shorter than the gate oxide layer, and is close to the third segment.
-
公开(公告)号：US12262523B2
公开(公告)日：2025-03-25
申请号：US17818537
申请日：2022-08-09
Inventor： Deyuan Xiao , Yong Yu , Guangsu Shao
IPC: H10B12/00
Abstract: The present disclosure provides a manufacturing method of a semiconductor structure and a semiconductor structure. The manufacturing method of a semiconductor structure includes: providing a substrate; forming a plurality of silicon pillars on the substrate, where the silicon pillars are arranged as an array; preprocessing the silicon pillar to form an active pillar, where the active pillar includes a first segment, a second segment, and a third segment; forming a first gate oxide layer on sidewalls of the second segment and the third segment; and forming a second gate oxide layer on the first gate oxide layer, where a length of the second gate oxide layer is less than that of the first gate oxide layer, and a thickness of the second gate oxide layer is greater than that of the first gate oxide layer.
-
公开(公告)号：US20230422467A1
公开(公告)日：2023-12-28
申请号：US17934647
申请日：2022-09-23
Inventor： Deyuan XIAO , Yong Yu , Guangsu Shao
IPC: H01L27/108
CPC classification number: H01L27/10873 , H01L27/10814
Abstract: The present disclosure is applicable to the field of semiconductors, and provides a transistor, a fabrication method, and a memory. The transistor includes: a semiconductor substrate, silicon support pillars, located on the semiconductor substrate, and gates, each of the gates arranged around one of the silicon support pillars. A side surface of each of the gates close to the silicon support pillar is a first surface, a side surface of each of the gates distant from the silicon support pillar is a second surface, and the length of the first surface is less than the length of the second surface. The length of the first surface of each of the gates is less than the length of the channel region of each of the silicon support pillars.
-
8.发明公开公开(公告)号：US20230301070A1
公开(公告)日：2023-09-21
申请号：US17872117
申请日：2022-07-25
Inventor： Deyuan Xiao , Yong Yu , Guangsu Shao
IPC: H01L27/108
CPC classification number: H01L27/10841 , H01L27/10864
Abstract: Provided are a semiconductor structure and a method for manufacturing the same, a memory device and a method for manufacturing the same. The semiconductor structure includes at least one transistor. Each of the at least one transistor includes a channel including a first semiconductor layer and a second semiconductor layer disposed around the first semiconductor layer. The second semiconductor layer introduces strain into the channel.
-
-
-
-
-
-
-
Search Results
8
records
(took 0.017 seconds)
