公开(公告)号：US20250112807A1

公开(公告)日：2025-04-03

申请号：US18904924

申请日：2024-10-02

Applicant: California Institute of Technology

Inventor： Adrian J. Tang ,  Goutam Chattopadhyay ,  Omkar Pradhan ,  Subash Khanal

IPC: H04L27/00 ,  H04B1/10

Abstract: A circuit comprising a first Fourier Transform block operable to perform a Fourier Transform and having a first input configured for receiving an I signal and a second input configured for receiving a Q signal; a first plurality of n of outputs for I channels and Q channels each comprising a different frequency bin output from the Fourier Transform; I and Q summing blocks comprising a set of connector lines connecting an ith one of I channels with an ith one of the Q channels; an inverse Fourier Transform block connected to the summing blocks and operable to perform an inverse Fourier Transform; a correlator for correlating the outputs of the inverse Fourier Transform; a Fourier Transform block for Fourier Transforming the correlator output; a comparator for comparing the correlation term to zero; and an error correction circuit for tuning the magnitude and phase of the I and Q channels using the comparator output as feedback.