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    Two modes of a configuration interface of a network ASIC
    2.
    发明授权
    Two modes of a configuration interface of a network ASIC 有权

    公开(公告)号：US09990324B2

    公开(公告)日：2018-06-05

    申请号：US14521354

    申请日：2014-10-22

    Applicant: CAVIUM, INC.

    Inventor： Guy Townsend Hutchison ,  Harish Krishnamoorthy ,  Gerald Schmidt ,  Vishal Anand

    IPC: G06F13/40 ,  G06F13/42

    CPC classification number: G06F13/4068 ,  G06F13/4221

    Abstract: Embodiments of the present invention are directed to a configuration interface of a network ASIC. The configuration interface allows for two modes of traversal of nodes. The nodes form one or more chains. Each chain is in a ring or a list topology. A master receives external access transactions. Once received by the master, an external access transaction traverses the chains to reach a target node. A target node either is an access to a memory space or is a module. A chain can include at least one decoder. A decoder includes logic that determines which of its leaves to send an external access transaction to. In contrast, if a module is not the target node, then the module passes an external access transaction to the next node coupled thereto; otherwise, if the module is the target node, the transmission of the external access transaction stops at the module.

    TWO MODES OF A CONFIGURATION INTERFACE OF A NETWORK ASIC
    4.
    发明申请
    TWO MODES OF A CONFIGURATION INTERFACE OF A NETWORK ASIC 审中-公开

    公开(公告)号：US20180246836A1

    公开(公告)日：2018-08-30

    申请号：US15969681

    申请日：2018-05-02

    Applicant: Cavium Inc.

    Inventor： Guy Townsend Hutchison ,  Harish Krishnamoorthy ,  Gerald Schmidt ,  Vishal Anand

    IPC: G06F13/40 ,  G06F13/42

    Abstract: Embodiments of the present invention are directed to a configuration interface of a network ASIC. The configuration interface allows for two modes of traversal of nodes. The nodes form one or more chains. Each chain is in a ring or a list topology. A master receives external access transactions. Once received by the master, an external access transaction traverses the chains to reach a target node. A target node either is an access to a memory space or is a module. A chain can include at least one decoder. A decoder includes logic that determines which of its leaves to send an external access transaction to. In contrast, if a module is not the target node, then the module passes an external access transaction to the next node coupled thereto; otherwise, if the module is the target node, the transmission of the external access transaction stops at the module.

    Smart holding registers to enable multiple register accesses
    5.
    发明授权
    Smart holding registers to enable multiple register accesses 有权
    智能保持寄存器以启用多个寄存器访问

    公开(公告)号：US09542342B2

    公开(公告)日：2017-01-10

    申请号：US14521359

    申请日：2014-10-22

    Applicant: CAVIUM, INC.

    Inventor： Vishal Anand ,  Harish Krishnamoorthy ,  Guy Townsend Hutchison

    IPC: G06F12/00 ,  G06F13/16 ,  G06F9/52 ,  G06F9/30

    CPC classification number: G06F13/1663 ,  G06F9/30098 ,  G06F9/52

    Abstract: A multiple access mechanism allows sources to simultaneously access different target registers at the same time without using a semaphore. The multiple access mechanism is implemented using N holding registers and source identifiers. The N holding registers are located in each slave engine. Each of the N holding registers is associated with a source and is configured to receive partial updates from the source before pushing the full update to a target register. After the source is finished updating the holding register and the holding register is ready to commit to the target register, a source identifier is added to a register bus. The source identifier identifies the holding register as the originator of the transaction on the register bus. The N holding registers are able to simultaneously handle N register transactions. The max value of N is 2n, where n is the number of bits in the source identifier.

    Abstract translation: 多访问机制允许源同时访问不同目标寄存器，而不使用信号量。 使用N个保持寄存器和源标识符来实现多址机制。 N个保持寄存器位于每个从动引擎中。 N个保持寄存器中的每一个与源相关联，并且被配置为在将完整更新推送到目标寄存器之前从源接收部分更新。 在源更新保持寄存器并且保持寄存器准备好提交到目标寄存器之后，源标识符被添加到寄存器总线。 源标识符将保持寄存器标识为寄存器总线上事务的发起者。 N个保持寄存器能够同时处理N个寄存器事务。 N的最大值为2n，其中n是源标识符中的位数。

    Method of implementing a network ASIC in a network device
    6.
    发明授权
    Method of implementing a network ASIC in a network device 有权

    公开(公告)号：US10579573B2

    公开(公告)日：2020-03-03

    申请号：US15969681

    申请日：2018-05-02

    Applicant: Cavium Inc.

    Inventor： Guy Townsend Hutchison ,  Harish Krishnamoorthy ,  Gerald Schmidt ,  Vishal Anand

    IPC: G06F13/40 ,  G06F13/42

    Abstract: Embodiments of the present invention are directed to a configuration interface of a network ASIC. The configuration interface allows for two modes of traversal of nodes. The nodes form one or more chains. Each chain is in a ring or a list topology. A master receives external access transactions. Once received by the master, an external access transaction traverses the chains to reach a target node. A target node either is an access to a memory space or is a module. A chain can include at least one decoder. A decoder includes logic that determines which of its leaves to send an external access transaction to. In contrast, if a module is not the target node, then the module passes an external access transaction to the next node coupled thereto; otherwise, if the module is the target node, the transmission of the external access transaction stops at the module.

    Multiple-interrupt propagation scheme in a network ASIC
    7.
    发明授权
    Multiple-interrupt propagation scheme in a network ASIC 有权

    公开(公告)号：US10078605B2

    公开(公告)日：2018-09-18

    申请号：US14521367

    申请日：2014-10-22

    Applicant: CAVIUM, INC.

    Inventor： Vishal Anand ,  Harish Krishnamoorthy ,  Guy Townsend Hutchison ,  Gerald Schmidt

    IPC: G06F13/26

    CPC classification number: G06F13/26

    Abstract: Embodiments of the present invention are directed to a multiple-interrupt propagation scheme, which is an automated mechanism for the specification and creation of interrupts. Interrupts originating at leaf nodes of a network chip are categorized into different service levels according to their interrupt types and are propagated to a master of the network chip via a manager. For each interrupt, depending on its service level, the manager either instantaneously propagates the interrupt or delays propagation of the interrupt to the master. The master forwards the interrupts to different destinations. A destination can be a processing element that is located on the network chip or externally on a different chip.

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