Two modes of a configuration interface of a network ASIC

    公开(公告)号:US09990324B2

    公开(公告)日:2018-06-05

    申请号:US14521354

    申请日:2014-10-22

    Applicant: CAVIUM, INC.

    CPC classification number: G06F13/4068 G06F13/4221

    Abstract: Embodiments of the present invention are directed to a configuration interface of a network ASIC. The configuration interface allows for two modes of traversal of nodes. The nodes form one or more chains. Each chain is in a ring or a list topology. A master receives external access transactions. Once received by the master, an external access transaction traverses the chains to reach a target node. A target node either is an access to a memory space or is a module. A chain can include at least one decoder. A decoder includes logic that determines which of its leaves to send an external access transaction to. In contrast, if a module is not the target node, then the module passes an external access transaction to the next node coupled thereto; otherwise, if the module is the target node, the transmission of the external access transaction stops at the module.

    Session based packet mirroring in a network ASIC

    公开(公告)号:US09760418B2

    公开(公告)日:2017-09-12

    申请号:US14494229

    申请日:2014-09-23

    Applicant: CAVIUM, INC.

    CPC classification number: G06F11/00 H04L45/16 H04L45/54 H04L49/201

    Abstract: A forwarding pipeline of a forwarding engine includes a mirror bit mask vector with one bit per supported independent mirror session. Each bit in the mirror bit mask vector can be set at any point in the forwarding pipeline when the forwarding engine determines that conditions for a corresponding mirror session are met. At the end of the forwarding pipeline, if any of the bits in the mirror bit mask vector is set, then a packet, the mirror bit mask vector and a pointer to the start of a mirror destination linked list are forwarded to the multicast replication engine. The mirror destination linked list typically defines a rule for mirroring. The multicast replication engine mirrors the packet according to the mirror destination linked list and the mirror bit mask vector.

    Apparatus and a method of detecting errors on registers

    公开(公告)号:US10656992B2

    公开(公告)日:2020-05-19

    申请号:US14521333

    申请日:2014-10-22

    Applicant: CAVIUM, INC.

    Abstract: An error detection circuit on a semiconductor chip detects whether soft errors have affected flip-flop implemented registers on the semiconductor chip. A signature of these flip-flop implemented registers on the semiconductor chip is periodically captured. The signature allows for the integrity of the flip-flop implemented registers to be constantly monitored. A soft error occurring on any of the flip-flop implemented registers can be immediately detected. In response to the detection, an interrupt is raised to notify software to take action.

    Fast hardware switchover in a control path in a network ASIC

    公开(公告)号:US10341130B2

    公开(公告)日:2019-07-02

    申请号:US15642141

    申请日:2017-07-05

    Applicant: Cavium, Inc.

    Abstract: A multicast destination table contains a list of links. The list of links includes the main link that is currently in use and alternate links to reach the same destination. The links in the list of links are ordered based on a metric. Each of the links is stored as an entry in the multicast destination table. A multicast replication engine traverses the list of links until an enabled link in the list of links is reached, and replicates a packet according to data associated with the enabled link in the list of links.

    Method of implementing a network ASIC in a network device

    公开(公告)号:US10579573B2

    公开(公告)日:2020-03-03

    申请号:US15969681

    申请日:2018-05-02

    Applicant: Cavium Inc.

    Abstract: Embodiments of the present invention are directed to a configuration interface of a network ASIC. The configuration interface allows for two modes of traversal of nodes. The nodes form one or more chains. Each chain is in a ring or a list topology. A master receives external access transactions. Once received by the master, an external access transaction traverses the chains to reach a target node. A target node either is an access to a memory space or is a module. A chain can include at least one decoder. A decoder includes logic that determines which of its leaves to send an external access transaction to. In contrast, if a module is not the target node, then the module passes an external access transaction to the next node coupled thereto; otherwise, if the module is the target node, the transmission of the external access transaction stops at the module.

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