公开(公告)号：US09000569B2

公开(公告)日：2015-04-07

申请号：US14042976

申请日：2013-10-01

Applicant: Chipbond Technology Corporation

Inventor： Chin-Tang Hsieh ,  You-Ming Hsu ,  Ming-Sheng Liu ,  Chih-Ping Wang

IPC: H01L21/4763 ,  H01L23/00 ,  H01L23/28 ,  H01L23/532 ,  H01L23/31

CPC classification number: H01L23/562 ,  H01L23/28 ,  H01L23/3192 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure includes a carrier, a first protective layer, a second protective layer, and a third protective layer. A first surface of the first protective layer comprises a first anti-stress zone. A first extension line from a first bottom edge intersects with a second extension line from a second bottom edge to form a first base point. A first projection line is formed on the first surface, an extension line of the first projection line intersects with the second bottom edge to form a first intersection point, a second projection line is formed on the first surface, and an extension line of the second projection line intersects with the first bottom edge to form a second intersection point. A zone by connecting the first base point, the first intersection point and the second intersection point is the first anti-stress zone.

Abstract translation: 半导体结构包括载体，第一保护层，第二保护层和第三保护层。 第一保护层的第一表面包括第一抗应力区。 来自第一底部边缘的第一延伸线与第二延伸线从第二底部边缘相交以形成第一基点。 第一投影线形成在第一表面上，第一投影线的延长线与第二底边缘相交形成第一交点，第二投影线形成在第一表面上，第二投影线形成在第二表面的延伸线上 投影线与第一底边相交形成第二交点。 通过连接第一基点，第一交点和第二交点的区域是第一抗应力区域。

公开(公告)号：US08981536B1

公开(公告)日：2015-03-17

申请号：US14048078

申请日：2013-10-08

Applicant: Chipbond Technology Corporation

Inventor： Chin-Tang Hsieh ,  You-Ming Hsu ,  Ming-Sheng Liu ,  Chih-Ping Wang

IPC: H01L29/06 ,  H01L23/58 ,  H01L23/495 ,  H01L23/00 ,  H01L29/02

CPC classification number: H01L23/562 ,  H01L23/31 ,  H01L23/3192 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure includes a carrier, a first protective layer, a second protective layer, and a third protective layer. A first surface of the first protective layer comprises a first anti-stress zone. The second protective layer reveals the first anti-stress zone and comprises a second surface, a first lateral side, a second lateral side and a first connection side. The second surface comprises a second anti-stress zone. An extension line of the first lateral side intersects with an extension line of the second lateral side to form a first intersection point. A zone formed by connecting the first intersection point and two points of the first connection side is the first anti-stress zone. The third protective layer reveals the second anti-stress zone and comprises a second connection side projected on the first surface to form a projection line parallel to the first connection side.

Abstract translation: 半导体结构包括载体，第一保护层，第二保护层和第三保护层。 第一保护层的第一表面包括第一抗应力区。 第二保护层揭示第一抗应力区，并包括第二表面，第一横向侧，第二横向侧和第一连接侧。 第二表面包括第二抗应力区。 第一侧面的延伸线与第二侧面的延伸线相交形成第一交点。 通过连接第一交点和第一连接侧的两个点形成的区域是第一抗应力区域。 第三保护层显示第二抗应力区域，并且包括突出在第一表面上的第二连接侧，以形成平行于第一连接侧的突出线。

公开(公告)号：US20150069584A1

公开(公告)日：2015-03-12

申请号：US14042976

申请日：2013-10-01

Applicant: Chipbond Technology Corporation

Inventor： Chin-Tang Hsieh ,  You-Ming Hsu ,  Ming-Sheng Liu ,  Chih-Ping Wang

IPC: H01L23/00

CPC classification number: H01L23/562 ,  H01L23/28 ,  H01L23/3192 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure includes a carrier, a first protective layer, a second protective layer, and a third protective layer. A first surface of the first protective layer comprises a first anti-stress zone. A first extension line from a first bottom edge intersects with a second extension line from a second bottom edge to form a first base point. A first projection line is formed on the first surface, an extension line of the first projection line intersects with the second bottom edge to form a first intersection point, a second projection line is formed on the first surface, and an extension line of the second projection line intersects with the first bottom edge to form a second intersection point. A zone by connecting the first base point, the first intersection point and the second intersection point is the first anti-stress zone.

Abstract translation: 半导体结构包括载体，第一保护层，第二保护层和第三保护层。 第一保护层的第一表面包括第一抗应力区。 来自第一底部边缘的第一延伸线与第二延伸线从第二底部边缘相交以形成第一基点。 第一投影线形成在第一表面上，第一投影线的延长线与第二底边缘相交形成第一交点，第二投影线形成在第一表面上，第二投影线形成在第二表面的延伸线上 投影线与第一底边相交形成第二交点。 通过连接第一基点，第一交点和第二交点的区域是第一抗应力区域。

公开(公告)号：US20150091141A1

公开(公告)日：2015-04-02

申请号：US14048078

申请日：2013-10-08

Applicant: CHIPBOND TECHNOLOGY CORPORATION

Inventor： Chin-Tang Hsieh ,  You-Ming Hsu ,  Ming-Sheng Liu ,  Chih-Ping Wang

IPC: H01L23/00 ,  H01L29/02

CPC classification number: H01L23/562 ,  H01L23/31 ,  H01L23/3192 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure includes a carrier, a first protective layer, a second protective layer, and a third protective layer. A first surface of the first protective layer comprises a first anti-stress zone. The second protective layer reveals the first anti-stress zone and comprises a second surface, a first lateral side, a second lateral side and a first connection side. The second surface comprises a second anti-stress zone. An extension line of the first lateral side intersects with an extension line of the second lateral side to form a first intersection point. A zone formed by connecting the first intersection point and two points of the first connection side is the first anti-stress zone. The third protective layer reveals the second anti-stress zone and comprises a second connection side projected on the first surface to form a projection line parallel to the first connection side.

Abstract translation: 半导体结构包括载体，第一保护层，第二保护层和第三保护层。 第一保护层的第一表面包括第一抗应力区。 第二保护层揭示第一抗应力区，并包括第二表面，第一横向侧，第二横向侧和第一连接侧。 第二表面包括第二抗应力区。 第一侧面的延伸线与第二侧面的延伸线相交形成第一交点。 通过连接第一交点和第一连接侧的两个点形成的区域是第一抗应力区域。 第三保护层显示第二抗应力区域，并且包括突出在第一表面上的第二连接侧，以形成平行于第一连接侧的突出线。