公开(公告)号：US20150279960A1

公开(公告)日：2015-10-01

申请号：US14740436

申请日：2015-06-16

Applicant: Choong-Ho Lee ,  Donggu Yi ,  Seung Chul Lee ,  Hyungsuk Lee ,  Seonah Nam ,  Changwoo Oh ,  Jongwook Lee ,  Song-Yi Han

Inventor： Choong-Ho Lee ,  Donggu Yi ,  Seung Chul Lee ,  Hyungsuk Lee ,  Seonah Nam ,  Changwoo Oh ,  Jongwook Lee ,  Song-Yi Han

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/762 ,  H01L21/3205

CPC classification number: H01L29/6681 ,  H01L21/02255 ,  H01L21/32053 ,  H01L21/76224 ,  H01L27/092 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: Provided are field effect transistors and methods of fabricating the same. The transistor may include a substrate with an active pattern, the active pattern having a top surface and two sidewalls, a gate electrode proximal to the top surface and the sidewalls of the active pattern and crossing the active pattern, a gate spacer covering a sidewall of the gate electrode, a gate dielectric pattern at a bottom surface of the gate electrode, a source electrode on the active pattern at one side of the gate electrode, a drain electrode on the active pattern at another side of the gate electrode, and silicide patterns on surfaces of the source and drain electrodes, respectively. The gate dielectric pattern includes at least one high-k layer and the gate spacer has a dielectric constant that is smaller than that of the gate dielectric pattern.

Abstract translation: 提供场效应晶体管及其制造方法。 晶体管可以包括具有有源图案的衬底，有源图案具有顶表面和两个侧壁，靠近顶表面的栅极电极和有源图案的侧壁并与有源图案交叉，栅极间隔件覆盖侧壁 栅极电极，栅电极的底面的栅极电介质图案，位于栅电极一侧的有源图案上的源电极，栅电极另一侧的有源图案上的漏电极，以及硅化物图案 分别在源电极和漏电极的表面上。 栅极电介质图案包括至少一个高k层，并且栅极间隔物的介电常数小于栅极电介质图案的介电常数。

公开(公告)号：US09121095B2

公开(公告)日：2015-09-01

申请号：US12784804

申请日：2010-05-21

Applicant: Choong-Ho Lee ,  Jung-Min Lee

Inventor： Choong-Ho Lee ,  Jung-Min Lee

IPC: C23C16/44 ,  C23C14/24 ,  C23C16/04

CPC classification number: C23C14/04 ,  C23C14/24 ,  C23C14/243 ,  C23C16/04 ,  C23C16/042 ,  Y10T29/49826 ,  Y10T29/49828

Abstract: A thin film deposition apparatus used to produce large substrates on a mass scale and improve manufacturing yield. The thin film deposition apparatus includes a deposition source; a first nozzle disposed at a side of the deposition source and including a plurality of first slits arranged in a first direction; a second nozzle disposed opposite to the first nozzle and including a plurality of second slits arranged in the first direction; and a barrier wall assembly including a plurality of barrier walls arranged in the first direction so as to partition a space between the first nozzle and the second nozzle.

Abstract translation: 一种薄膜沉积装置，用于大规模生产大型基板并提高制造产量。 薄膜沉积设备包括沉积源; 第一喷嘴，其设置在所述沉积源的一侧，并且包括沿第一方向布置的多个第一狭缝; 第二喷嘴，与所述第一喷嘴相对设置并且包括沿所述第一方向布置的多个第二狭缝; 以及阻挡壁组件，其包括沿所述第一方向布置的多个阻挡壁，以便分隔所述第一喷嘴和所述第二喷嘴之间的空间。

公开(公告)号：US09035285B2

公开(公告)日：2015-05-19

申请号：US13069254

申请日：2011-03-22

Applicant: Jung-Min Lee ,  Choong-Ho Lee ,  Kie Hyun Nam

Inventor： Jung-Min Lee ,  Choong-Ho Lee ,  Kie Hyun Nam

IPC: H01L51/52 ,  H01L27/32 ,  H01L51/00 ,  B82Y10/00

CPC classification number: H01L51/524 ,  B82Y10/00 ,  H01L27/3258 ,  H01L27/3276 ,  H01L51/0048 ,  H01L51/5243 ,  H01L51/5246 ,  H01L51/525

Abstract: A display device includes a substrate, a display unit formed on the substrate, a sealing substrate bonded to the substrate by a bonding layer surrounding the display unit, the sealing substrate comprising a complex member and an insulating member, wherein the complex member has a resin matrix and a plurality of carbon fibers and the insulator is connected to an edge of the complex member and comprises a penetration hole, a metal layer disposed at one side of the sealing substrate wherein the one side faces the substrate, and a conductive connection unit filling in the penetration hole and contacting the metal layer. The complex member and the insulator may be coupled by tongue and groovecoupling along a thickness direction of the sealing substrate where the protrusion-groove coupling structure is top-to-bottom symmetric and the insulator may have a thickness identical to that of the complex member.

Abstract translation: 显示装置包括基板，形成在基板上的显示单元，通过围绕显示单元的接合层粘合到基板的密封基板，密封基板包括复合部件和绝缘部件，其中复合部件具有树脂 基体和多个碳纤维，绝缘体连接到复合构件的边缘，并且包括穿透孔，设置在密封基板的一侧的金属层，其中一侧面向基板，以及导电连接单元填充 在穿透孔中并与金属层接触。 复合构件和绝缘体可以沿着密封衬底的厚度方向通过舌和槽耦合来耦合，其中突出沟槽联接结构是从上到下对称的，并且绝缘体可以具有与复合构件的厚度相同的厚度。

公开(公告)号：US08519549B2

公开(公告)日：2013-08-27

申请号：US12889290

申请日：2010-09-23

Applicant: Jung-Min Lee ,  Choong-Ho Lee

Inventor： Jung-Min Lee ,  Choong-Ho Lee

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: C09J9/02 ,  C08K9/02 ,  C09J7/20 ,  C09J2203/326 ,  C09J2205/102 ,  H01L27/3276 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/81191 ,  H01L2224/81903 ,  H01L2224/83851 ,  H01L2224/9211 ,  H01L2924/12044 ,  H01L2924/1461 ,  Y10T428/25 ,  H01L2924/00

Abstract: An anisotropic conductive film (ACF) is disclosed. The ACF includes a film, an adhesive layer positioned on the film, and one or more conductive balls within the adhesive layer. The conductive balls include a first core part having a first hardness, a second core part covering the first core part and having a second hardness that is greater than the first hardness, and a conductive part covering the second core part, respectively.

Abstract translation: 公开了各向异性导电膜（ACF）。 ACF包括膜，位于膜上的粘合剂层和粘合剂层内的一个或多个导电球。 导电球包括具有第一硬度的第一芯部，覆盖第一芯部的第二芯部，并且具有大于第一硬度的第二硬度，以及分别覆盖第二芯部的导电部。

公开(公告)号：US08466470B2

公开(公告)日：2013-06-18

申请号：US12870019

申请日：2010-08-27

Applicant: Jung-Min Lee ,  Choong-Ho Lee

Inventor： Jung-Min Lee ,  Choong-Ho Lee

IPC: H01L27/14

CPC classification number: H01L27/3276 ,  H05K3/323 ,  H05K2201/0133 ,  H05K2201/0221 ,  H05K2201/0338 ,  H05K2201/10674

Abstract: A display device includes a wire substrate including a wire unit for driving the display device, an integrated circuit chip mounted at the wire substrate, and a pad unit extended from the wire unit to be disposed between the wire substrate and the integrated circuit chip. The pad unit is connected to the integrated circuit chip. The pad unit includes a first conductive layer extended from the wire unit, and a second conductive layer disposed on the first conductive layer. The hardness of the second conductive layer is less than the hardness of the first conductive layer.

Abstract translation: 显示装置包括：线基板，包括用于驱动显示装置的线单元，安装在线基板上的集成电路芯片;以及从布线单元延伸以设置在线基板和集成电路芯片之间的焊盘单元。 焊盘单元连接到集成电路芯片。 焊盘单元包括从导线单元延伸的第一导电层和设置在第一导电层上的第二导电层。 第二导电层的硬度小于第一导电层的硬度。

公开(公告)号：US08264034B2

公开(公告)日：2012-09-11

申请号：US13178308

申请日：2011-07-07

Applicant: Keun-Nam Kim ,  Hung-Mo Yang ,  Choong-Ho Lee

Inventor： Keun-Nam Kim ,  Hung-Mo Yang ,  Choong-Ho Lee

IPC: H01L27/088

CPC classification number: H01L29/7854 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/4236 ,  H01L29/66621 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/7856

Abstract: A fin field effect transistor (fin FET) is formed using a bulk silicon substrate and sufficiently guarantees a top channel length formed under a gate, by forming a recess having a predetermined depth in a fin active region and then by forming the gate in an upper part of the recess. A device isolation film is formed to define a non-active region and a fin active region in a predetermined region of the substrate. In a portion of the device isolation film a first recess is formed, and in a portion of the fin active region a second recess having a depth shallower than the first recess is formed. A gate insulation layer is formed within the second recess, and a gate is formed in an upper part of the second recess. A source/drain region is formed in the fin active region of both sides of a gate electrode.

Abstract translation: 使用体硅衬底形成鳍状场效应晶体管（鳍FET），并通过在翅片有源区中形成具有预定深度的凹槽，然后通过在上部形成栅极来充分保证形成在栅极下方的顶部沟道长度 部分休息。 形成器件隔离膜以在衬底的预定区域中限定非有源区和鳍有源区。 在器件隔离膜的一部分中，形成第一凹部，并且在翅片有源区域的一部分中形成有比第一凹部浅的深度的第二凹部。 栅极绝缘层形成在第二凹部内，栅极形成在第二凹部的上部。 源极/漏极区域形成在栅电极的两侧的鳍片有源区域中。

公开(公告)号：US20120015512A1

公开(公告)日：2012-01-19

申请号：US13238084

申请日：2011-09-21

Applicant: Suk-Kang SUNG ,  Choong-Ho Lee ,  Dong-Uk Choi ,  Hee-Soo Kang

Inventor： Suk-Kang SUNG ,  Choong-Ho Lee ,  Dong-Uk Choi ,  Hee-Soo Kang

IPC: H01L21/28

CPC classification number: H01L27/11568

Abstract: A non-volatile memory device includes field insulating layer patterns on a substrate to define an active region of the substrate, upper portions of the field insulating layer patterns protruding above an upper surface of the substrate, a tunnel insulating layer on the active region, a charge trapping layer on the tunnel insulating layer, a blocking layer on the charge trapping layer, first insulating layers on upper surfaces of the field insulating layer patterns, and a word line structure on the blocking layer and first insulating layers.

Abstract translation: 非易失性存储器件包括在衬底上的场绝缘层图案，以限定衬底的有源区，场绝缘层图案的上部突出在衬底的上表面上，在有源区上的隧道绝缘层， 隧道绝缘层上的电荷俘获层，电荷俘获层上的阻挡层，场绝缘层图案的上表面上的第一绝缘层，以及阻挡层和第一绝缘层上的字线结构。

公开(公告)号：US08072804B2

公开(公告)日：2011-12-06

申请号：US12471729

申请日：2009-05-26

Applicant: Se-Hoon Lee ,  Choong-Ho Lee ,  Jung-Dal Choi

Inventor： Se-Hoon Lee ,  Choong-Ho Lee ,  Jung-Dal Choi

IPC: G11C11/34

CPC classification number: G11C11/5628 ,  G11C2211/5641

Abstract: A non-volatile memory device includes an array of non-volatile memory cells configured to support single bit and multi-bit programming states. A control circuit is provided, which is configured to program a first page of non-volatile memory cells in the array as M-bit cells during a first programming operation and further configured to program the first page of non-volatile memory cells as N-bit cells during a second programming operation. The first and second programming operations are separated in time by at least one operation to erase the first page of non-volatile memory cells. M and N are unequal integers greater than zero.

Abstract translation: 非易失性存储器件包括被配置为支持单位和多位编程状态的非易失性存储器单元的阵列。 提供了一种控制电路，其被配置为在第一编程操作期间将阵列中的第一页非易失性存储单元编程为M位单元，并且还被配置为将第一页非易失性存储单元编程为N- 在第二次编程操作期间。 第一和第二编程操作通过至少一个擦除非易失性存储器单元的第一页的操作在时间上被分离。 M和N是不等于零的整数。

公开(公告)号：US20110265714A1

公开(公告)日：2011-11-03

申请号：US13025084

申请日：2011-02-10

Applicant: Choong-Ho Lee ,  Jung-Min Lee

Inventor： Choong-Ho Lee ,  Jung-Min Lee

IPC: B05C11/00

CPC classification number: C23C14/042 ,  C23C14/04

Abstract: A mask frame assembly includes a frame, a mask having a deposition pattern and being installable on the frame in a state of being pulled by a first tension force in a first direction, and a tension force applying portion in the mask and configured to apply a second tension force in a second direction that is perpendicular or substantially perpendicular to the first direction.

Abstract translation: 荫罩框架组件包括框架，具有沉积图案的掩模，并且可在第一方向上以第一张力拉动的状态下安装在框架上;以及张力施加部分， 在与第一方向垂直或基本垂直的第二方向上的第二张力。

公开(公告)号：US20110260227A1

公开(公告)日：2011-10-27

申请号：US13178308

申请日：2011-07-07

Applicant: Keun-Nam Kim ,  Hung-Mo Yang ,  Choong-Ho Lee

Inventor： Keun-Nam Kim ,  Hung-Mo Yang ,  Choong-Ho Lee

IPC: H01L29/78

CPC classification number: H01L29/7854 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/4236 ,  H01L29/66621 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/7856

Abstract: A fin field effect transistor (fin FET) is formed using a bulk silicon substrate and sufficiently guarantees a top channel length formed under a gate, by forming a recess having a predetermined depth in a fin active region and then by forming the gate in an upper part of the recess. A device isolation film is formed to define a non-active region and a fin active region in a predetermined region of the substrate. In a portion of the device isolation film a first recess is formed, and in a portion of the fin active region a second recess having a depth shallower than the first recess is formed. A gate insulation layer is formed within the second recess, and a gate is formed in an upper part of the second recess. A source/drain region is formed in the fin active region of both sides of a gate electrode.

Abstract translation: 使用体硅衬底形成鳍状场效应晶体管（鳍FET），并通过在翅片有源区中形成具有预定深度的凹槽，然后通过在上部形成栅极来充分保证形成在栅极下方的顶部沟道长度 部分休息。 形成器件隔离膜以在衬底的预定区域中限定非有源区和鳍有源区。 在器件隔离膜的一部分中，形成第一凹部，并且在翅片有源区域的一部分中形成有比第一凹部浅的深度的第二凹部。 栅极绝缘层形成在第二凹部内，栅极形成在第二凹部的上部。 源极/漏极区域形成在栅电极的两侧的鳍片有源区域中。