公开(公告)号：US09281292B2

公开(公告)日：2016-03-08

申请号：US13532119

申请日：2012-06-25

Applicant: Chuan Hu ,  Vijay Nair

Inventor： Chuan Hu ,  Vijay Nair

IPC: H01L23/34 ,  H01L23/00 ,  H01L25/03 ,  H01L25/16 ,  H01L21/56

CPC classification number: H01L24/97 ,  H01L21/563 ,  H01L21/565 ,  H01L21/568 ,  H01L21/768 ,  H01L21/78 ,  H01L24/11 ,  H01L24/19 ,  H01L24/73 ,  H01L24/81 ,  H01L24/96 ,  H01L25/03 ,  H01L25/16 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81191 ,  H01L2224/83385 ,  H01L2224/97 ,  H01L2924/12042 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/181 ,  H01L2924/19011 ,  H01L2924/3011 ,  Y10T29/49124 ,  Y10T29/4913 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/85 ,  H01L2924/00014

Abstract: In one embodiment of the invention, a system in package (SiP) is described which includes a plurality of device components with different form factors embedded within a molding compound layer. A surface for each of the device components is coplanar with a surface of the molding compound layer, and a single redistribution layer (RDL) formed on the coplanar surfaces of the molding compound layer and the plurality of device components. An active device die is electrically bonded to the single RDL directly vertically adjacent the plurality of device components. In an embodiment, the SiP is electrically connected to a circuit board with the active device die between the single RDL and the circuit board. In an embodiment, the SiP is electrically connected to a circuit board with the active device die over the single RDL and the circuit board.

Abstract translation: 在本发明的一个实施例中，描述了一种包装系统（SiP），其包括嵌入在模塑料层内的具有不同形状因素的多个装置部件。 用于每个器件部件的表面与模制化合物层的表面共面，并且在模制化合物层和多个器件部件的共面表面上形成单个再分布层（RDL）。 有源器件管芯直接与多个器件部件垂直地电连接到单个RDL。 在一个实施例中，SiP电连接到电路板，其中有源器件管芯在单个RDL和电路板之间。 在一个实施例中，SiP电连接到电路板，有源器件裸片在单个RDL和电路板上。

公开(公告)号：US20150008595A1

公开(公告)日：2015-01-08

申请号：US14493718

申请日：2014-09-23

Applicant: Chuan Hu

Inventor： Chuan Hu

IPC: H01L23/00

CPC classification number: H01L24/05 ,  H01L21/561 ,  H01L21/568 ,  H01L24/11 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/82 ,  H01L2221/68381 ,  H01L2224/02381 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/24137 ,  H01L2224/82002 ,  H01L2224/8203 ,  H01L2224/821 ,  H01L2224/96 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/35 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2224/82 ,  H01L2224/11 ,  H01L2924/014 ,  H01L2924/00

Abstract: This disclosure relates generally to a semiconductor device and method of making the semiconductor device by pressing an electrical contact of a chip into a bonding layer on a carrier. The bonding layer is cured and coupled, at least in part, to the electrical contact. A molding layer is applied in contact with the chip and a first major surface of the bonding layer. Distribution circuitry is coupled to the electrical contact.

Abstract translation: 本公开总体上涉及通过将芯片的电接触压入载体上的接合层来制造半导体器件的半导体器件和方法。 粘合层固化并至少部分地耦合到电接触。 施加与芯片接触的成型层和接合层的第一主表面。 分配电路耦合到电触点。

公开(公告)号：US20140293529A1

公开(公告)日：2014-10-02

申请号：US13853977

申请日：2013-03-29

Applicant: Vijay K. Nair ,  Chuan Hu ,  Shawna M. Liff ,  Larry E. Mosley

Inventor： Vijay K. Nair ,  Chuan Hu ,  Shawna M. Liff ,  Larry E. Mosley

IPC: H01Q1/22 ,  H01L23/04 ,  G06F1/16

CPC classification number: H01Q7/06 ,  G06F1/16 ,  H01F1/0054 ,  H01L21/565 ,  H01L21/568 ,  H01L23/295 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/66 ,  H01L24/17 ,  H01L24/19 ,  H01L24/96 ,  H01L2223/6672 ,  H01L2223/6677 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2924/01029 ,  H01L2924/05442 ,  H01L2924/12042 ,  H01L2924/1421 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/181 ,  H01L2924/186 ,  H01L2924/19011 ,  H01L2924/19042 ,  H01L2924/19102 ,  H01L2924/19105 ,  H01Q1/2283 ,  H01Q1/2291 ,  H01Q23/00 ,  H01L2924/00

Abstract: A method apparatus and material are described for radio frequency passives and antennas. In one example, an electronic component has a synthesized magnetic nanocomposite material with aligned magnetic domains, a conductor embedded within the nanocomposite material, and contact pads extending through the nanocomposite material to connect to the conductor.

Abstract translation: 无线电频率无源和天线描述了一种方法装置和材料。 在一个示例中，电子部件具有具有对准磁畴的合成磁性纳米复合材料，嵌入在纳米复合材料内的导体以及延伸穿过纳米复合材料以连接到导体的接触垫。

公开(公告)号：US20140001629A1

公开(公告)日：2014-01-02

申请号：US13995479

申请日：2011-12-21

Applicant: Chuan Hu

Inventor： Chuan Hu

IPC: H01L23/373 ,  H01L21/48

CPC classification number: H01L23/3736 ,  H01L21/4871 ,  H01L23/3128 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/12105 ,  H01L2224/73267 ,  H01L2224/97 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/18162 ,  H01L2924/00 ,  H01L2224/82

Abstract: Packaged semiconductor die and CTE-engineering die pairs and methods to form packaged semiconductor die and CTE-engineering die pairs are described. For example, a semiconductor package includes a substrate. A semiconductor die is embedded in the substrate and has a surface area. A CTE-engineering die is embedded in the substrate and coupled to the semiconductor die. The CTE-engineering die has a surface area the same and in alignment with the surface area of the semiconductor die.

Abstract translation: 描述了封装的半导体管芯和CTE工程管芯对以及形成封装的半导体管芯和CTE工程管芯对的方法。 例如，半导体封装包括衬底。 半导体管芯被嵌入基板中并具有表面积。 将CTE工程管芯嵌入衬底并耦合到半导体管芯。 CTE工程模具的表面积相同并与半导体管芯的表面积对准。

公开(公告)号：US20130343022A1

公开(公告)日：2013-12-26

申请号：US13532119

申请日：2012-06-25

Applicant: Chuan Hu ,  Vijay Nair

Inventor： Chuan Hu ,  Vijay Nair

IPC: H01L25/16 ,  H05K3/32 ,  H05K13/00

CPC classification number: H01L24/97 ,  H01L21/563 ,  H01L21/565 ,  H01L21/568 ,  H01L21/768 ,  H01L21/78 ,  H01L24/11 ,  H01L24/19 ,  H01L24/73 ,  H01L24/81 ,  H01L24/96 ,  H01L25/03 ,  H01L25/16 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81191 ,  H01L2224/83385 ,  H01L2224/97 ,  H01L2924/12042 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/181 ,  H01L2924/19011 ,  H01L2924/3011 ,  Y10T29/49124 ,  Y10T29/4913 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/85 ,  H01L2924/00014

Abstract: In one embodiment of the invention, a system in package (SiP) is described which includes a plurality of device components with different form factors embedded within a molding compound layer. A surface for each of the device components is coplanar with a surface of the molding compound layer, and a single redistribution layer (RDL) formed on the coplanar surfaces of the molding compound layer and the plurality of device components. An active device die is electrically bonded to the single RDL directly vertically adjacent the plurality of device components. In an embodiment, the SiP is electrically connected to a circuit board with the active device die between the single RDL and the circuit board. In an embodiment, the SiP is electrically connected to a circuit board with the active device die over the single RDL and the circuit board.

Abstract translation: 在本发明的一个实施例中，描述了一种包装系统（SiP），其包括嵌入在模塑料层内的具有不同形状因素的多个装置部件。 用于每个器件部件的表面与模制化合物层的表面共面，并且在模制化合物层和多个器件部件的共面表面上形成单个再分布层（RDL）。 有源器件管芯直接与多个器件部件垂直地电连接到单个RDL。 在一个实施例中，SiP电连接到电路板，其中有源器件管芯在单个RDL和电路板之间。 在一个实施例中，SiP电连接到电路板，有源器件裸片在单个RDL和电路板上。

公开(公告)号：US20110147059A1

公开(公告)日：2011-06-23

申请号：US12653722

申请日：2009-12-17

Applicant: Qing Ma ,  Chuan Hu ,  Patrick Morrow

Inventor： Qing Ma ,  Chuan Hu ,  Patrick Morrow

IPC: H05K1/03 ,  B05D5/12 ,  B32B37/00

CPC classification number: H01L23/49822 ,  B32B2457/08 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/3675 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/16227 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2224/81815 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01011 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01016 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01024 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/05442 ,  H01L2924/14 ,  H01L2924/15184 ,  H01L2924/15788 ,  H01L2924/16251 ,  H05K3/42 ,  H05K3/4605 ,  H05K2201/0195 ,  H05K2201/096 ,  Y10T156/10 ,  H01L2924/00

Abstract: Disclosed are embodiments of a substrate for an integrated circuit (IC) device. The substrate includes a core comprised of two or more discrete glass layers that have been bonded together. A separate bonding layer may be disposed between adjacent glass layers to couple these layers together. The substrate may also include build-up structures on opposing sides of the multi-layer glass core, or perhaps on one side of the core. Electrically conductive terminals may be formed on both sides of the substrate, and an IC die may be coupled with the terminals on one side of the substrate. The terminals on the opposing side may be coupled with a next-level component, such as a circuit board. One or more conductors extend through the multi-layer glass core, and one or more of the conductors may be electrically coupled with the build-up structures disposed over the core. Other embodiments are described and claimed.

Abstract translation: 公开了用于集成电路（IC）装置的基板的实施例。 衬底包括由已经结合在一起的两个或更多个离散的玻璃层组成的芯。 可以在相邻的玻璃层之间设置单独的粘合层，以将这些层连接在一起。 衬底还可以包括在多层玻璃芯的相对侧上或者可能在芯的一侧上的堆积结构。 导电端子可以形成在基板的两侧，并且IC管芯可以与基板的一侧上的端子耦合。 相对侧上的端子可以与诸如电路板的下一级组件耦合。 一个或多个导体延伸通过多层玻璃芯，并且一个或多个导体可以与布置在芯上的积聚结构电耦合。 描述和要求保护其他实施例。

公开(公告)号：US07626251B2

公开(公告)日：2009-12-01

申请号：US11529851

申请日：2006-09-29

Applicant: Daoqiang Lu ,  Chuan Hu ,  Dongming He

Inventor： Daoqiang Lu ,  Chuan Hu ,  Dongming He

IPC: H01L23/10

CPC classification number: H01L23/433 ,  H01L21/563 ,  H01L23/3735 ,  H01L2924/0002 ,  H01L2924/16152 ,  H01L2924/00

Abstract: A microelectronic die assembly. The die assembly includes a microelectronic die, and a thermally conductive element attached to the backside of the die with a thermal interface material. The thermally conductive element has lateral dimensions smaller than, substantially equal to, or larger than lateral dimensions of the die by up to a maximum amount, wherein the maximum amount is adapted to allow a mounting of the die assembly to a package substrate.

Abstract translation: 微电子模组件。 模具组件包括微电子管芯和导热元件，其通过热界面材料附接到管芯的背面。 导热元件的横向尺寸小于，基本上等于或大于模具的横向尺寸直到最大量，其中最大量适于允许将模具组件安装到封装衬底。

公开(公告)号：US07397119B2

公开(公告)日：2008-07-08

申请号：US11295623

申请日：2005-12-06

Applicant: Gregory M. Chrysler ,  Chuan Hu

Inventor： Gregory M. Chrysler ,  Chuan Hu

IPC: H01L23/34

CPC classification number: H01L21/4882 ,  H01L21/78 ,  H01L23/3732 ,  H01L23/3735 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/274 ,  H01L2224/73253 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/15312 ,  H01L2924/00

Abstract: An embodiment of the present invention is a technique to heat spread at wafer level. A silicon wafer is thinned. A chemical vapor deposition diamond (CVDD) wafer processed. The CVDD wafer is bonded to the thinned silicon wafer to form a bonded wafer. Metallization is plated on back side of the CVDD wafer. The CVDD wafer is reflowed to flatten the back side.

Abstract translation: 本发明的一个实施例是一种在晶片级散热的技术。 硅晶片变薄。 化学气相沉积金刚石（CVDD）晶圆处理。 CVDD晶片被结合到变薄的硅晶片以形成接合晶片。 金属化电镀在CVDD晶片的背面。 CVDD晶片被回流以使背面变平。

公开(公告)号：US20080153209A1

公开(公告)日：2008-06-26

申请号：US12042392

申请日：2008-03-05

Applicant: Cheng-Yi Liu ,  Johanna Swan ,  Steven Towle ,  Anna George ,  Chuan Hu

Inventor： Cheng-Yi Liu ,  Johanna Swan ,  Steven Towle ,  Anna George ,  Chuan Hu

IPC: H01L21/58

CPC classification number: H01L24/97 ,  H01L21/4871 ,  H01L23/142 ,  H01L23/36 ,  H01L23/367 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/11 ,  H01L24/19 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/04105 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/20 ,  H01L2224/211 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2224/82039 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01051 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/013

Abstract: A method and apparatus provide an integrated circuit package with improved heat dissipation and easier fabrication. The integrated circuit package includes a thinned semiconductor die attached to a heat spreader using a thermally conductive material. The thinned die reduces the thermal resistance of the die/heat spreader combination to improve heat extraction from the die as well as eliminating processing steps in fabrication. Additionally, the thinned die becomes more compliant as it takes on the thermal/mechanical properties of the heat spreader to reduce stress-induced cracking of the die.

Abstract translation: 一种方法和装置提供具有改进的散热和更容易制造的集成电路封装。 集成电路封装包括使用导热材料附着到散热器的薄化半导体管芯。 减薄的模头降低了模具/散热器组合的热阻，以改善从模具的热提取以及消除制造中的加工步骤。 此外，薄型模具变得更加柔顺，因为它承受散热器的热/机械性能，以减少模具的应力引起的开裂。

公开(公告)号：US20080142954A1

公开(公告)日：2008-06-19

申请号：US11641164

申请日：2006-12-19

Applicant: Chuan Hu

Inventor： Chuan Hu

IPC: H01L23/34

CPC classification number: H01L25/0655 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/1461 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A multi-chip package may include at least one integrated circuit die disposed on a substrate, and a local heat spreader is thermally coupled with the die. A global heat spreader is thermally coupled with this local heat spreader. The global heat spreader may also be coupled with one or more other local heat spreaders that are each coupled with another die disposed in the multi-chip package. Other embodiments are described and may be claimed.

Abstract translation: 多芯片封装可以包括设置在基板上的至少一个集成电路管芯，并且局部散热器与管芯热耦合。 全球散热器与本地散热器热耦合。 全球散热器还可以与一个或多个其它本地散热器耦合，每个散热器各自与设置在多芯片封装中的另一个管芯耦合。 描述并且可以要求保护其他实施例。