公开(公告)号：US20230056019A1

公开(公告)日：2023-02-23

申请号：US17982224

申请日：2022-11-07

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Neil WHYTE ,  Andy BREWSTER ,  Jens PUCHERT

IPC: G06F11/30 ,  G06F11/07 ,  G06F11/16 ,  G06F13/24 ,  G06F13/42

Abstract: A device, comprising: a main module; a plurality of secondary modules; and a data bus configured to enable data transmission between the main module and the plurality of secondary modules over a data line of the data bus; wherein each of the plurality of secondary modules is configured with a unique secondary address used by the main module to communicate with the respective secondary module over the data line, wherein the main module is operable to configure a first two or more of the plurality of secondary modules with a first common secondary address for simultaneous data transmission from the main module to the first two or more of the plurality of secondary modules over the data line.

公开(公告)号：US20220171691A1

公开(公告)日：2022-06-02

申请号：US17106324

申请日：2020-11-30

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Neil WHYTE ,  Andy BREWSTER ,  Jens PUCHERT

IPC: G06F11/30 ,  G06F11/07 ,  G06F11/16 ,  G06F13/42 ,  G06F13/24

Abstract: A device, comprising: a main module; a plurality of secondary modules; and a data bus configured to enable data transmission between the main module and the plurality of secondary modules over a data line of the data bus; wherein each of the plurality of secondary modules is configured with a unique secondary address used by the main module to communicate with the respective secondary module over the data line, wherein the main module is operable to configure a first two or more of the plurality of secondary modules with a first common secondary address for simultaneous data transmission from the main module to the first two or more of the plurality of secondary modules over the data line.