公开(公告)号：US20230056019A1

公开(公告)日：2023-02-23

申请号：US17982224

申请日：2022-11-07

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Neil WHYTE ,  Andy BREWSTER ,  Jens PUCHERT

IPC: G06F11/30 ,  G06F11/07 ,  G06F11/16 ,  G06F13/24 ,  G06F13/42

Abstract: A device, comprising: a main module; a plurality of secondary modules; and a data bus configured to enable data transmission between the main module and the plurality of secondary modules over a data line of the data bus; wherein each of the plurality of secondary modules is configured with a unique secondary address used by the main module to communicate with the respective secondary module over the data line, wherein the main module is operable to configure a first two or more of the plurality of secondary modules with a first common secondary address for simultaneous data transmission from the main module to the first two or more of the plurality of secondary modules over the data line.

公开(公告)号：US20220171691A1

公开(公告)日：2022-06-02

申请号：US17106324

申请日：2020-11-30

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Neil WHYTE ,  Andy BREWSTER ,  Jens PUCHERT

IPC: G06F11/30 ,  G06F11/07 ,  G06F11/16 ,  G06F13/42 ,  G06F13/24

Abstract: A device, comprising: a main module; a plurality of secondary modules; and a data bus configured to enable data transmission between the main module and the plurality of secondary modules over a data line of the data bus; wherein each of the plurality of secondary modules is configured with a unique secondary address used by the main module to communicate with the respective secondary module over the data line, wherein the main module is operable to configure a first two or more of the plurality of secondary modules with a first common secondary address for simultaneous data transmission from the main module to the first two or more of the plurality of secondary modules over the data line.

公开(公告)号：US20240283237A1

公开(公告)日：2024-08-22

申请号：US18413633

申请日：2024-01-16

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Michael ROBINSON ,  Ross C. MORGAN ,  Graham G. MACKAY ,  Neil WHYTE

IPC: H02H3/24 ,  G01R31/327 ,  G01R31/64 ,  H03K17/687

CPC classification number: H02H3/24 ,  H03K17/6871 ,  G01R31/3277 ,  G01R31/64

Abstract: An integrated circuit (IC) comprising: control circuitry operable to control: an external switch of a primary current path for an energy storage component of a circuit, wherein the external switch of the primary current path is external to the IC; a first internal switch of a secondary current path for the energy storage element, wherein the first internal switch is internal to the IC, wherein the IC is operable in: a first mode in which the first internal switch of the secondary current path is actuated to enable the secondary current path; and a second mode in which the external switch of the primary current path is actuated to enable the primary current path.

公开(公告)号：US20220229937A1

公开(公告)日：2022-07-21

申请号：US17394014

申请日：2021-08-04

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Michael CHANDLER-PAGE ,  Pradeep SAMINATHAN ,  Jon EKLUND ,  Neil WHYTE ,  José Arnaldo BIANCO FILHO ,  Abhinav SHARMA

IPC: G06F21/71 ,  G06F9/4401

Abstract: An integrated circuit comprises first and second interfaces, an internal addressable space comprising a plurality of address ranges, and a control unit. Each of the first and second interfaces is coupled to the internal addressable space via the control unit. The control unit is configurable in a first state in which the control unit is configured to allow or deny the second interface access to a subset of the plurality of address ranges of the internal addressable space.

公开(公告)号：US20220229784A1

公开(公告)日：2022-07-21

申请号：US17232514

申请日：2021-04-16

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Neil WHYTE ,  Michael CHANDLER-PAGE ,  Pradeep SAMINATHAN ,  Jon EKLUND

IPC: G06F12/14 ,  G06F13/16

Abstract: An integrated circuit comprises first and second interfaces, an internal addressable space comprising a plurality of address ranges, and a control unit. Each of the first and second interfaces is coupled to the internal addressable space via the control unit. The control unit is configurable in a first state in which the control unit is configured to allow or deny the second interface access to a subset of the plurality of address ranges of the internal addressable space.