公开(公告)号：US20220285299A1

公开(公告)日：2022-09-08

申请号：US17748817

申请日：2022-05-19

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Yaoyu PANG ,  Steven A. ATHERTON

IPC: H01L23/00

Abstract: A semiconductor die may be coupled to a printed circuit board using a solder ball. The semiconductor die comprises a redistribution layer formed above a semiconductor chip, a polymer layer formed on the redistribution layer, and an Under Bump Metallurgy (UBM) layer formed on the polymer layer. The polymer layer comprises a plurality of vias, which electrically couple the UBM layer to the redistribution layer. The entire UBM layer may be deposited with a continuously flat upper surface for coupling to the solder ball. The plurality of vias may be positioned such that they are centered on a point that is not central to the UBM layer.

公开(公告)号：US20230088252A1

公开(公告)日：2023-03-23

申请号：US17993638

申请日：2022-11-23

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Craig MCADAM ,  Jonathan TAYLOR ,  Douglas MACFARLANE ,  John KERR ,  James MUNGER ,  John PAVELKA ,  Steven A. ATHERTON

IPC: H01L23/498 ,  H01L23/00

Abstract: The present disclosure relates to a chip scale package (CSP) comprising: a first set of CSP contact balls or bumps; a second set of CSP contact balls or bumps; and a channel routing region, the channel routing region being devoid of any CSP contact balls or bumps.

公开(公告)号：US20220246514A1

公开(公告)日：2022-08-04

申请号：US17245259

申请日：2021-04-30

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Craig MCADAM ,  Jonathan TAYLOR ,  Douglas MACFARLANE ,  John KERR ,  James MUNGER ,  John PAVELKA ,  Steven A. ATHERTON

IPC: H01L23/498 ,  H01L23/00

Abstract: The present disclosure relates to a chip scale package (CSP) comprising: a first set of CSP contact balls or bumps; a second set of CSP contact balls or bumps; and a channel routing region, the channel routing region being devoid of any CSP contact balls or bumps.

公开(公告)号：US20200343206A1

公开(公告)日：2020-10-29

申请号：US16857606

申请日：2020-04-24

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Yaoyu PANG ,  Steven A. ATHERTON

IPC: H01L23/00

Abstract: A semiconductor die may be coupled to a printed circuit board using a solder ball. The semiconductor die comprises a redistribution layer formed above a semiconductor chip, a polymer layer formed on the redistribution layer, and an Under Bump Metallurgy (UBM) layer formed on the polymer layer. The polymer layer comprises a plurality of vias, which electrically couple the UBM layer to the redistribution layer. The entire UBM layer may be deposited with a continuously flat upper surface for coupling to the solder ball. The plurality of vias may be positioned such that they are centered on a point that is not central to the UBM layer.