公开(公告)号：US09844135B2

公开(公告)日：2017-12-12

申请号：US14480430

申请日：2014-09-08

Applicant: Cisco Technology, Inc.

Inventor： Feng Wu ,  Yongchao Ji ,  Yang Tang ,  Stephen Scearce ,  Shunjia Liu ,  Shaochun Tang

IPC: H05K7/00 ,  H05K1/11 ,  H05K1/02 ,  H05K1/18 ,  H05K3/34

CPC classification number: H05K1/115 ,  H05K1/0231 ,  H05K1/113 ,  H05K1/114 ,  H05K1/181 ,  H05K3/3415 ,  H05K3/3436 ,  H05K2201/09227 ,  H05K2201/09609 ,  H05K2201/10015 ,  H05K2201/10674

Abstract: Various implementations disclosed herein include arrangements that reduce parasitic inductance associated with a discrete decoupling capacitor by using a three-terminal capacitor and a staggered array of power supply and ground connections. In some implementations, a capacitive decoupling arrangement includes a substrate, an array of electrical vias of first and second types, and a capacitive arrangement on one side of the substrate coupled to the array of electrical vias. The array of electrical vias includes a first type of vias and a second type of vias. The capacitive arrangement is coupled between two respective vias of the first type of vias and two respective vias of the second type of vias on the first planar surface of the substrate. The capacitive arrangement includes a plurality of capacitive elements electrically arranged in parallel between the two respective vias of the first type of vias and the two respective vias of the second type of vias.

公开(公告)号：US20160073500A1

公开(公告)日：2016-03-10

申请号：US14480430

申请日：2014-09-08

Applicant: Cisco Technology, Inc.

Inventor： Feng Wu ,  Yongchao Ji ,  Yang Tang ,  Stephen Scearce ,  Shunjia Liu ,  Shaochun Tang

IPC: H05K1/11 ,  H05K1/18

CPC classification number: H05K1/115 ,  H05K1/0231 ,  H05K1/113 ,  H05K1/114 ,  H05K1/181 ,  H05K3/3415 ,  H05K3/3436 ,  H05K2201/09227 ,  H05K2201/09609 ,  H05K2201/10015 ,  H05K2201/10674

Abstract: Various implementations disclosed herein include arrangements that reduce parasitic inductance associated with a discrete decoupling capacitor by using a three-terminal capacitor and a staggered array of power supply and ground connections. In some implementations, a capacitive decoupling arrangement includes a substrate, an array of electrical vias of first and second types, and a capacitive arrangement on one side of the substrate coupled to the array of electrical vias. The array of electrical vias includes a first type of vias and a second type of vias. The capacitive arrangement is coupled between two respective vias of the first type of vias and two respective vias of the second type of vias on the first planar surface of the substrate. The capacitive arrangement includes a plurality of capacitive elements electrically arranged in parallel between the two respective vias of the first type of vias and the two respective vias of the second type of vias.

Abstract translation: 本文公开的各种实施方案包括通过使用三端电容器和电源和接地连接的交错阵列来减少与离散去耦电容器相关联的寄生电感的布置。 在一些实施方式中，电容去耦装置包括衬底，第一和第二类型的电通路的阵列，以及耦合到电气通孔阵列的衬底的一侧的电容布置。 电气通孔阵列包括第一类型的通孔和第二类型的通孔。 电容布置耦合在第一类型的通孔的两个相应的通孔和衬底的第一平面表面上的第二类型的通孔的两个相应的通孔之间。 电容性布置包括多个电容元件，它们并联布置在第一类型通孔的两个相应的通孔和第二类型通孔的两个相应的通孔之间。